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JPS5553921A - Booster circuit - Google Patents

Booster circuit

Info

Publication number
JPS5553921A
JPS5553921A JP12796578A JP12796578A JPS5553921A JP S5553921 A JPS5553921 A JP S5553921A JP 12796578 A JP12796578 A JP 12796578A JP 12796578 A JP12796578 A JP 12796578A JP S5553921 A JPS5553921 A JP S5553921A
Authority
JP
Japan
Prior art keywords
vss
vdd
period
signal
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12796578A
Other languages
Japanese (ja)
Other versions
JPS601977B2 (en
Inventor
Kenichi Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP53127965A priority Critical patent/JPS601977B2/en
Publication of JPS5553921A publication Critical patent/JPS5553921A/en
Publication of JPS601977B2 publication Critical patent/JPS601977B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Liquid Crystal Display Device Control (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
  • Liquid Crystal (AREA)

Abstract

PURPOSE: To realize a thin-gage and long-life digital electronic watch featuring multiple functions by eliminating the useless pierced current at the booster circuit and thus increasing the efficiency of the booster circuit.
CONSTITUTION: N-channel gate G5 is turned on when input signal ϕ5 features -VSS1, and thus capacitor C3 is charged up to (VDD-VSS1) volts. Under these conditions, N-channel gate G6 is off, and as a result the charge stored in capacitor C4 is never set free. When signal ϕ5 changes to VDD from -VSS1 (period of t3) and immediately before signal ϕ5 changes to VSS1 from VDD (period of t4), control signal ϕ7 is supplied. And gate G5 is turned off when signal ϕ5 changes to VDD from VSS1, but P-channel FETTP7 is off and N-channel FETTN7 is on respectively during the period of t3. Thus gate G6 is turned off. Thus no pierced current flows since gates G5 and G6 are off during the period of t3.
COPYRIGHT: (C)1980,JPO&Japio
JP53127965A 1978-10-18 1978-10-18 boost circuit Expired JPS601977B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53127965A JPS601977B2 (en) 1978-10-18 1978-10-18 boost circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53127965A JPS601977B2 (en) 1978-10-18 1978-10-18 boost circuit

Publications (2)

Publication Number Publication Date
JPS5553921A true JPS5553921A (en) 1980-04-19
JPS601977B2 JPS601977B2 (en) 1985-01-18

Family

ID=14973049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53127965A Expired JPS601977B2 (en) 1978-10-18 1978-10-18 boost circuit

Country Status (1)

Country Link
JP (1) JPS601977B2 (en)

Also Published As

Publication number Publication date
JPS601977B2 (en) 1985-01-18

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