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JPS5553747A - Computer of order pre-fetch system - Google Patents

Computer of order pre-fetch system

Info

Publication number
JPS5553747A
JPS5553747A JP12655178A JP12655178A JPS5553747A JP S5553747 A JPS5553747 A JP S5553747A JP 12655178 A JP12655178 A JP 12655178A JP 12655178 A JP12655178 A JP 12655178A JP S5553747 A JPS5553747 A JP S5553747A
Authority
JP
Japan
Prior art keywords
order
processor
address
buffer
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12655178A
Other languages
Japanese (ja)
Inventor
Yoshinari Nakasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12655178A priority Critical patent/JPS5553747A/en
Publication of JPS5553747A publication Critical patent/JPS5553747A/en
Pending legal-status Critical Current

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  • Advance Control (AREA)

Abstract

PURPOSE: To send the address information of the execution order to each processor for the computer which executes the machin order row by the plural units of processors and in the pipe-line system by installing the internal order memory device and the order address memory device.
CONSTITUTION: The order address is sent to program memory device 3 storing the machine word order row and the operand from 1st processor 1 to read out the machine order row. The order is stored in internal order buffer 5 in processor 1, and furthermore the address detection is carried out for the order code to store the address in order address buffer 6. Then 2nd processor 2 receives the order from buffer 5 and carries out the fixed process. In case the overflow or other errors occur in processor 2 at the operation time, the process condition of processor 2 plus the order address from buffer 6 are sent to process part 4. At part 4 the effectiveness or the like is decided for the process result based on the information sent in to decide the process to be executed next and to investigate the career of the order executed at processor 2.
COPYRIGHT: (C)1980,JPO&Japio
JP12655178A 1978-10-13 1978-10-13 Computer of order pre-fetch system Pending JPS5553747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12655178A JPS5553747A (en) 1978-10-13 1978-10-13 Computer of order pre-fetch system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12655178A JPS5553747A (en) 1978-10-13 1978-10-13 Computer of order pre-fetch system

Publications (1)

Publication Number Publication Date
JPS5553747A true JPS5553747A (en) 1980-04-19

Family

ID=14937966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12655178A Pending JPS5553747A (en) 1978-10-13 1978-10-13 Computer of order pre-fetch system

Country Status (1)

Country Link
JP (1) JPS5553747A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197546A (en) * 1982-05-13 1983-11-17 Mitsubishi Electric Corp Compensating device for instruction queue
JPS6125254A (en) * 1984-07-13 1986-02-04 Hitachi Ltd Program debug system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197546A (en) * 1982-05-13 1983-11-17 Mitsubishi Electric Corp Compensating device for instruction queue
JPS6125254A (en) * 1984-07-13 1986-02-04 Hitachi Ltd Program debug system

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