[go: up one dir, main page]

JPS5552652A - Frame synchronizing unit - Google Patents

Frame synchronizing unit

Info

Publication number
JPS5552652A
JPS5552652A JP12652278A JP12652278A JPS5552652A JP S5552652 A JPS5552652 A JP S5552652A JP 12652278 A JP12652278 A JP 12652278A JP 12652278 A JP12652278 A JP 12652278A JP S5552652 A JPS5552652 A JP S5552652A
Authority
JP
Japan
Prior art keywords
pattern
circuit
hunting
collation
generated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12652278A
Other languages
Japanese (ja)
Other versions
JPS585543B2 (en
Inventor
Sunao Sato
Masahiro Ko
Makoto Kawashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP53126522A priority Critical patent/JPS585543B2/en
Publication of JPS5552652A publication Critical patent/JPS5552652A/en
Publication of JPS585543B2 publication Critical patent/JPS585543B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To obtain a frame synchronizing unit which does not generate step for burst code errors, etc., and is synchronized in a short time by the hunting action even in case of step out. CONSTITUTION:Input is applied to pattern collation circuit 17 from terminal 12 and is successively shifted to perform collation with a synchronizing pattern for every bit 1; and if pattern agreement is detected, output D is generated. Meanwhile, the address of the pattern agreement bit is held in latch 23; and when all three bits agree with synchronizing patterns, pulse J is generated. Control circuit 28 executes operations such as initialization of frame counter 14 on a basis of the pattern collation result from circuit 17, the address collation result from gate 27 and the counted result of a back protection counter. When pulse K in circuit 28 is L-level, a hunting start point is indicated, and the Q output of FF33 is held at an H level. By repeating this hunting and back protection 19, step out is prevented; and even if step out is generated once, it is returned to a normal state immediately.
JP53126522A 1978-10-13 1978-10-13 frame synchronizer Expired JPS585543B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53126522A JPS585543B2 (en) 1978-10-13 1978-10-13 frame synchronizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53126522A JPS585543B2 (en) 1978-10-13 1978-10-13 frame synchronizer

Publications (2)

Publication Number Publication Date
JPS5552652A true JPS5552652A (en) 1980-04-17
JPS585543B2 JPS585543B2 (en) 1983-01-31

Family

ID=14937281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53126522A Expired JPS585543B2 (en) 1978-10-13 1978-10-13 frame synchronizer

Country Status (1)

Country Link
JP (1) JPS585543B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5765050A (en) * 1980-10-07 1982-04-20 Fujitsu Ltd Measuring system for signal-to-noisde ratio
JPS57186859A (en) * 1981-05-13 1982-11-17 Nippon Telegr & Teleph Corp <Ntt> Frame synchronizing circuit
JPS58184843A (en) * 1982-04-02 1983-10-28 ジ−メンス・アクチエンゲゼルシヤフト Synchronizer for digital signal demultiplexing equipment
JPS61189041A (en) * 1985-02-15 1986-08-22 Nec Corp Signal deciding device
JPS627240A (en) * 1985-07-03 1987-01-14 Nec Corp Synchronization decision system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5765050A (en) * 1980-10-07 1982-04-20 Fujitsu Ltd Measuring system for signal-to-noisde ratio
JPS57186859A (en) * 1981-05-13 1982-11-17 Nippon Telegr & Teleph Corp <Ntt> Frame synchronizing circuit
JPS58184843A (en) * 1982-04-02 1983-10-28 ジ−メンス・アクチエンゲゼルシヤフト Synchronizer for digital signal demultiplexing equipment
JPS61189041A (en) * 1985-02-15 1986-08-22 Nec Corp Signal deciding device
JPS627240A (en) * 1985-07-03 1987-01-14 Nec Corp Synchronization decision system

Also Published As

Publication number Publication date
JPS585543B2 (en) 1983-01-31

Similar Documents

Publication Publication Date Title
SE432488B (en) DEVICE FOR PROCESSING DATA WITH PRIVACY
JPS5552652A (en) Frame synchronizing unit
JPS5633718A (en) Resetting method and its device for electronic control type controller
JPS5663633A (en) Character input device
RU2019907C1 (en) Programmable pulse generator
JPS5384654A (en) Error correction circuit having test function
JPS56116350A (en) Suprious noise generator for software discrimination demodulation
CA1085001A (en) Control pulse generators
SU617845A1 (en) Binary counter checking device
JPS53114325A (en) Control system of data processor
SU892687A1 (en) Pulse duration discriminator
SU700352A1 (en) Device for making the program of photographic type composition apparatus
SU964651A2 (en) Discrete communication channel simulator
JPS6153728B2 (en)
SU493902A1 (en) A device for generating a series of pulses
FR2406912A1 (en) Pulse sequence generation for memory testing - uses reverse counter supplied with starting values by its own memory
KR940009389B1 (en) Control code discrimination apparatus and method of remote control
SU1003354A1 (en) Rate scaler
SU1688242A2 (en) Random numbers generator
JPS53128228A (en) Keyboard control device
SU765795A2 (en) Pseudorandom number generator
SU1757089A1 (en) Shaper of duration of pulses
JPS55122300A (en) Memory check system
SU714630A1 (en) Pulse train generator
JPS5686390A (en) Electronic watch