JPS5537634A - Integrated-circuit device - Google Patents
Integrated-circuit deviceInfo
- Publication number
- JPS5537634A JPS5537634A JP11011878A JP11011878A JPS5537634A JP S5537634 A JPS5537634 A JP S5537634A JP 11011878 A JP11011878 A JP 11011878A JP 11011878 A JP11011878 A JP 11011878A JP S5537634 A JPS5537634 A JP S5537634A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- test
- line
- code
- rom1
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 101001106432 Homo sapiens Rod outer segment membrane protein 1 Proteins 0.000 abstract 3
- 102100021424 Rod outer segment membrane protein 1 Human genes 0.000 abstract 3
- 238000001514 detection method Methods 0.000 abstract 3
- 238000004886 process control Methods 0.000 abstract 2
- 230000006870 function Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Semiconductor Integrated Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE: To make it possible to check easily a process control code by building a memory part and a method of checking its contents on the same chip and by allowing the memory part to have the process control code and a test code, which are combined.
CONSTITUTION: Integrated-circuit device 8 consists of incorporated ROM1, detection circuit 2, holding circuit 3 set by a detection signal, terminal 4 which transfers an output signal from circuit 3, test circuit 5 which controls a test function, and control gates 6 and 7. For example, level "1" is written to a test code as to a line where there are odd-numbered levels "1" in bits constituting an instruction set to each line of ROM1, so that every line will have even-numbered levels "1" set without fail. By a test instruction from circuit 5, code data is read out to circuit 2 at every line of ROM1 and through a comparsion, it is decided whether the number of levels "1" is odd or even; when it is odd, an error in memory data is detected and a detection signal is outputted to circuit 3, thereby outputting a signal indicating the existence of the error to terminal 4 for a constant period.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11011878A JPS5537634A (en) | 1978-09-06 | 1978-09-06 | Integrated-circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11011878A JPS5537634A (en) | 1978-09-06 | 1978-09-06 | Integrated-circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5537634A true JPS5537634A (en) | 1980-03-15 |
Family
ID=14527485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11011878A Pending JPS5537634A (en) | 1978-09-06 | 1978-09-06 | Integrated-circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5537634A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57207347A (en) * | 1981-06-16 | 1982-12-20 | Mitsubishi Electric Corp | Semiconductor device |
| JPS60193056A (en) * | 1984-03-14 | 1985-10-01 | Nec Corp | Single chip microcomputer |
-
1978
- 1978-09-06 JP JP11011878A patent/JPS5537634A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57207347A (en) * | 1981-06-16 | 1982-12-20 | Mitsubishi Electric Corp | Semiconductor device |
| JPS60193056A (en) * | 1984-03-14 | 1985-10-01 | Nec Corp | Single chip microcomputer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE69704888D1 (en) | Control circuit for the data output for a semiconductor memory device with a pipeline structure | |
| JPS5321542A (en) | Error data memory circuit | |
| JPS5537634A (en) | Integrated-circuit device | |
| JPS5764396A (en) | Multi-processor | |
| JPS5634194A (en) | Memory unit | |
| JPS5690500A (en) | Semiconductor memory device | |
| JPS5526704A (en) | Two-dimentional sequential coding system | |
| JPS5353932A (en) | Fault detection system for memory address line | |
| JPS5542343A (en) | Control system for memory unit | |
| JPS5593596A (en) | Memory unit | |
| JPS578999A (en) | Memory controller | |
| JPS5443433A (en) | Memory element designation system | |
| JPS5882351A (en) | Memory device | |
| JPS5457924A (en) | Data input device | |
| JPS5617442A (en) | Parity error processing system | |
| JPS5727342A (en) | Error checking system for error detecting correcting circuit | |
| JPS5556264A (en) | Error detection circuit | |
| JPS57161563A (en) | Testing method for logical level generating circuit | |
| JPS55146550A (en) | High speed branch controlling system | |
| JPS53135536A (en) | Test method for data processor | |
| JPS5464939A (en) | Data transfer device | |
| JPS5528502A (en) | Memory device | |
| JPS6220047A (en) | Storage element | |
| JPS5667426A (en) | Processing system for failed data | |
| JPS55142479A (en) | Failure processing system for magnetic bubble memory |