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JPS5533257A - Status condition stop control system - Google Patents

Status condition stop control system

Info

Publication number
JPS5533257A
JPS5533257A JP10608778A JP10608778A JPS5533257A JP S5533257 A JPS5533257 A JP S5533257A JP 10608778 A JP10608778 A JP 10608778A JP 10608778 A JP10608778 A JP 10608778A JP S5533257 A JPS5533257 A JP S5533257A
Authority
JP
Japan
Prior art keywords
stop control
latches
control system
hardware
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10608778A
Other languages
Japanese (ja)
Inventor
Kazumasa Kimura
Koji Hayashi
Hitoshi Kaminomura
Minoru Sueyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10608778A priority Critical patent/JPS5533257A/en
Publication of JPS5533257A publication Critical patent/JPS5533257A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To obtain an effective system for exact debugging of hardware by freezing the state of a unit by stopping the clock of the unit when some of various control signals provided to the hardware meet assigned conditions.
CONSTITUTION: To a cyclic path of latches 2-0, 2-1..., single clock stop control circuit 5 is provided. Partitioned test conditions (a), (b) and (c) are set to test- condition setting register 6. For example, when pieces of control information A, B and C are set to latch 2-1 while cycling through latches 2-0, 2-1..., coincidence circuits 7A, 7B and 7C make checks on coincidences between A and (a), B and (b), and C and (c). When one of councidences is found, corresponding coincidence circuits 7A, 7B or 7C generates coincidence signal MA, MB or MC. Consequently, clock stop control curcuit 5 stops clocks.
COPYRIGHT: (C)1980,JPO&Japio
JP10608778A 1978-08-30 1978-08-30 Status condition stop control system Pending JPS5533257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10608778A JPS5533257A (en) 1978-08-30 1978-08-30 Status condition stop control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10608778A JPS5533257A (en) 1978-08-30 1978-08-30 Status condition stop control system

Publications (1)

Publication Number Publication Date
JPS5533257A true JPS5533257A (en) 1980-03-08

Family

ID=14424759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10608778A Pending JPS5533257A (en) 1978-08-30 1978-08-30 Status condition stop control system

Country Status (1)

Country Link
JP (1) JPS5533257A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6985980B1 (en) * 2000-11-03 2006-01-10 Xilinx, Inc. Diagnostic scheme for programmable logic in a system on a chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6985980B1 (en) * 2000-11-03 2006-01-10 Xilinx, Inc. Diagnostic scheme for programmable logic in a system on a chip

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