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JPS553092A - Microprogram control unit - Google Patents

Microprogram control unit

Info

Publication number
JPS553092A
JPS553092A JP7683978A JP7683978A JPS553092A JP S553092 A JPS553092 A JP S553092A JP 7683978 A JP7683978 A JP 7683978A JP 7683978 A JP7683978 A JP 7683978A JP S553092 A JPS553092 A JP S553092A
Authority
JP
Japan
Prior art keywords
address
shunting
subroutine
stores
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7683978A
Other languages
Japanese (ja)
Inventor
Yoshihisa Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7683978A priority Critical patent/JPS553092A/en
Publication of JPS553092A publication Critical patent/JPS553092A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate the waste process time when the subroutine is used continuously and repetitively by shunting the addresses returned from the subroutine to the two shunting means and then selecting the addresses for the shunting means.
CONSTITUTION: Microprogram memory means 1 stores the microprogram; microorder storing means 2 stores the microorder which controls various actions read out of means 1; and branch destination address shunting means 5 shunts and stores the address read out from inside means 2. In addition, adder 8 connected to switch circuit 6 is provided to add a constant number to the address of the branch destination order, along with address register 3 to supply the input of adder 8 plus address shunt register 4 to shunt the address of register 3. Thus, the order read out of means 2 is carried out via the return destination address of switch circuit 7 when the branching is given from the main routine to the subroutine.
COPYRIGHT: (C)1980,JPO&Japio
JP7683978A 1978-06-23 1978-06-23 Microprogram control unit Pending JPS553092A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7683978A JPS553092A (en) 1978-06-23 1978-06-23 Microprogram control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7683978A JPS553092A (en) 1978-06-23 1978-06-23 Microprogram control unit

Publications (1)

Publication Number Publication Date
JPS553092A true JPS553092A (en) 1980-01-10

Family

ID=13616833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7683978A Pending JPS553092A (en) 1978-06-23 1978-06-23 Microprogram control unit

Country Status (1)

Country Link
JP (1) JPS553092A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS575156A (en) * 1980-05-07 1982-01-11 Fairchild Camera Instr Co Interruptible microprogram sequence device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS575156A (en) * 1980-05-07 1982-01-11 Fairchild Camera Instr Co Interruptible microprogram sequence device
JPH0243212B2 (en) * 1980-05-07 1990-09-27

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