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JPS5519846A - Lead frame for resin sealed type semiconductor device - Google Patents

Lead frame for resin sealed type semiconductor device

Info

Publication number
JPS5519846A
JPS5519846A JP9259678A JP9259678A JPS5519846A JP S5519846 A JPS5519846 A JP S5519846A JP 9259678 A JP9259678 A JP 9259678A JP 9259678 A JP9259678 A JP 9259678A JP S5519846 A JPS5519846 A JP S5519846A
Authority
JP
Japan
Prior art keywords
lead frame
plate
layer
area
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9259678A
Other languages
Japanese (ja)
Inventor
Takeyumi Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9259678A priority Critical patent/JPS5519846A/en
Publication of JPS5519846A publication Critical patent/JPS5519846A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To do away with a film carrier to have only one process of bonding by protruding toward a chip placing area one side of Ni coated layer on a plate without a core.
CONSTITUTION: Photoresist masks 2, 2' are coated except the surface area remaining after the patterning of copper or copper alloy plate 1. Next, Ni plating layers 3, 3' are formed on a bare surface of the plate 1. In this case, the resist film 2' has been formed so that the Ni plating layer 3' is to have an inside-extending area 3" compared with the other plating layer 3. Next, resist 2, 2' are removed and the bare area of the plate 1 is removed with Ni plating layers 3, 3' as masks. Next, Sn or Au layer 4 is coated on Ni plating layers 3, 3' to form a lead frame 5. And, a chip 7 is placed into a chip placing area 6 with Ni plating layer 3" protruding, and heat pressure is applied through a bump 8. This lead frame 5 does not need a film carrier and make the process to be a bonding one only.
COPYRIGHT: (C)1980,JPO&Japio
JP9259678A 1978-07-31 1978-07-31 Lead frame for resin sealed type semiconductor device Pending JPS5519846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9259678A JPS5519846A (en) 1978-07-31 1978-07-31 Lead frame for resin sealed type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9259678A JPS5519846A (en) 1978-07-31 1978-07-31 Lead frame for resin sealed type semiconductor device

Publications (1)

Publication Number Publication Date
JPS5519846A true JPS5519846A (en) 1980-02-12

Family

ID=14058822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9259678A Pending JPS5519846A (en) 1978-07-31 1978-07-31 Lead frame for resin sealed type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5519846A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8288178B2 (en) * 2008-08-11 2012-10-16 Renesas Electronics Corporation Lead frame, method of manufacturing the same, and method of manufacturing semiconductor device
CN103752970A (en) * 2013-12-24 2014-04-30 广州金升阳科技有限公司 Lead frame soldering method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8288178B2 (en) * 2008-08-11 2012-10-16 Renesas Electronics Corporation Lead frame, method of manufacturing the same, and method of manufacturing semiconductor device
CN103752970A (en) * 2013-12-24 2014-04-30 广州金升阳科技有限公司 Lead frame soldering method

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