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JPS55164376A - Integrated circuit testing unit - Google Patents

Integrated circuit testing unit

Info

Publication number
JPS55164376A
JPS55164376A JP7323879A JP7323879A JPS55164376A JP S55164376 A JPS55164376 A JP S55164376A JP 7323879 A JP7323879 A JP 7323879A JP 7323879 A JP7323879 A JP 7323879A JP S55164376 A JPS55164376 A JP S55164376A
Authority
JP
Japan
Prior art keywords
circuit
testing unit
substrate
testing
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7323879A
Other languages
Japanese (ja)
Inventor
Yasushi Wada
Tsunetaka Sudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP7323879A priority Critical patent/JPS55164376A/en
Publication of JPS55164376A publication Critical patent/JPS55164376A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE: To make it possible to install many measuring terminals with a simple adjustment, by a constitution where a testing driving circuit and so on can be formed directly on the substrate, in the testing unit for the integrated circuit formed on the semiconductor wafer.
CONSTITUTION: Measured circuit 4 is integrated on chip 2 and is connected to measuring terminal 6 through metallic wiring 5. Though testing unit 7 is superposed onto this circuit, silicon is used for substrate 8 in testing unit 7, and bump 9 of alloy is caused to adhere onto the surface of substrate 8 as a probe terminal. First, positioning microscope 14 with a vidicon mounted and computer 15 are used to position sample stand 16. Next, testing unit 7 is superposed onto sample wafer 1 slowly, and electric connection is confirmed by edge sensor 11, and driver 12 is operated from the external to access measured circuit 4 in the arrow direction, and the output signal is gathered into receiver 13 and is subjected to the recognition processing in the external circuit. Since the testing driving circuit and so on can be formed directly on the substrate, many measuring terminals can be installed with a simple adjustment.
COPYRIGHT: (C)1980,JPO&Japio
JP7323879A 1979-06-11 1979-06-11 Integrated circuit testing unit Pending JPS55164376A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7323879A JPS55164376A (en) 1979-06-11 1979-06-11 Integrated circuit testing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7323879A JPS55164376A (en) 1979-06-11 1979-06-11 Integrated circuit testing unit

Publications (1)

Publication Number Publication Date
JPS55164376A true JPS55164376A (en) 1980-12-22

Family

ID=13512394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7323879A Pending JPS55164376A (en) 1979-06-11 1979-06-11 Integrated circuit testing unit

Country Status (1)

Country Link
JP (1) JPS55164376A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173451A (en) * 1991-06-04 1992-12-22 Micron Technology, Inc. Soft bond for semiconductor dies
US5336649A (en) * 1991-06-04 1994-08-09 Micron Technology, Inc. Removable adhesives for attachment of semiconductor dies
US5342807A (en) * 1991-06-04 1994-08-30 Micron Technology, Inc. Soft bond for semiconductor dies
US5894218A (en) * 1994-04-18 1999-04-13 Micron Technology, Inc. Method and apparatus for automatically positioning electronic dice within component packages

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991775A (en) * 1972-12-26 1974-09-02

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991775A (en) * 1972-12-26 1974-09-02

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173451A (en) * 1991-06-04 1992-12-22 Micron Technology, Inc. Soft bond for semiconductor dies
US5336649A (en) * 1991-06-04 1994-08-09 Micron Technology, Inc. Removable adhesives for attachment of semiconductor dies
US5342807A (en) * 1991-06-04 1994-08-30 Micron Technology, Inc. Soft bond for semiconductor dies
US5894218A (en) * 1994-04-18 1999-04-13 Micron Technology, Inc. Method and apparatus for automatically positioning electronic dice within component packages
US5955877A (en) * 1994-04-18 1999-09-21 Micron Technology, Inc. Method and apparatus for automatically positioning electronic dice within component packages
US6064194A (en) * 1994-04-18 2000-05-16 Micron Technology, Inc. Method and apparatus for automatically positioning electronic dice within component packages
US6150828A (en) * 1994-04-18 2000-11-21 Micron Technology, Inc. Method and apparatus for automatically positioning electronic dice with component packages
US6210984B1 (en) 1994-04-18 2001-04-03 Micron Technology, Inc. Method and apparatus for automatically positioning electronic dice within component packages
US6353312B1 (en) 1994-04-18 2002-03-05 Micron Technology, Inc. Method for positioning a semiconductor die within a temporary package
US6492187B1 (en) 1994-04-18 2002-12-10 Micron Technology, Inc. Method for automatically positioning electronic die within component packages

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