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JPS55162144A - Assigning circuit for number of digits of transmitted data - Google Patents

Assigning circuit for number of digits of transmitted data

Info

Publication number
JPS55162144A
JPS55162144A JP6978479A JP6978479A JPS55162144A JP S55162144 A JPS55162144 A JP S55162144A JP 6978479 A JP6978479 A JP 6978479A JP 6978479 A JP6978479 A JP 6978479A JP S55162144 A JPS55162144 A JP S55162144A
Authority
JP
Japan
Prior art keywords
signal
data
digits
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6978479A
Other languages
Japanese (ja)
Inventor
Yoshiki Takeo
Akinori Imai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anritsu Corp
Original Assignee
Anritsu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anritsu Corp filed Critical Anritsu Corp
Priority to JP6978479A priority Critical patent/JPS55162144A/en
Publication of JPS55162144A publication Critical patent/JPS55162144A/en
Pending legal-status Critical Current

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To make it possible to set the number of digits of transmitted data in accordance with an equipment by adding a terminator signal on detecting data, transmitted between an input-output equipment and data processor, being transmitted as much as the desired number of digits.
CONSTITUTION: The number SV of assigned digits of transmitted data assigned by digit-number assignment unit 1 and counted digits CV of input data UD sequentially counted by digit counter 2 are compared to each other by comparing circuit 3 and when both agree with each other, coincidence signal es is output. When signal CS is input terminator circuit 4, circuit 4 outputs reset signal RS to counter 2 to reset conter 2 and also outputs signal RS and terminator signal TS to output change- over circuit 5. While signal RS is not input, circuit 5 outputs transmitted data DS and when signal RS is input, data DS is stopped to output signal TS as output data DO. Therefore, data DO can be output with signal TS added following to the number of digits assigned by unit 1.
COPYRIGHT: (C)1980,JPO&Japio
JP6978479A 1979-06-04 1979-06-04 Assigning circuit for number of digits of transmitted data Pending JPS55162144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6978479A JPS55162144A (en) 1979-06-04 1979-06-04 Assigning circuit for number of digits of transmitted data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6978479A JPS55162144A (en) 1979-06-04 1979-06-04 Assigning circuit for number of digits of transmitted data

Publications (1)

Publication Number Publication Date
JPS55162144A true JPS55162144A (en) 1980-12-17

Family

ID=13412723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6978479A Pending JPS55162144A (en) 1979-06-04 1979-06-04 Assigning circuit for number of digits of transmitted data

Country Status (1)

Country Link
JP (1) JPS55162144A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62121857U (en) * 1986-12-18 1987-08-03
CN110875911A (en) * 2018-09-03 2020-03-10 厦门奇力微电子有限公司 Communication protocol and communication method for supporting automatic identification of single data packet data bit number

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5271949A (en) * 1975-12-12 1977-06-15 Hitachi Ltd Desirializer
JPS5279606A (en) * 1975-12-25 1977-07-04 Fujitsu Ltd Transmission control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5271949A (en) * 1975-12-12 1977-06-15 Hitachi Ltd Desirializer
JPS5279606A (en) * 1975-12-25 1977-07-04 Fujitsu Ltd Transmission control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62121857U (en) * 1986-12-18 1987-08-03
JPS6322752Y2 (en) * 1986-12-18 1988-06-22
CN110875911A (en) * 2018-09-03 2020-03-10 厦门奇力微电子有限公司 Communication protocol and communication method for supporting automatic identification of single data packet data bit number

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