JPS55160393A - Read voltage setting system for semiconductor memory - Google Patents
Read voltage setting system for semiconductor memoryInfo
- Publication number
- JPS55160393A JPS55160393A JP6817779A JP6817779A JPS55160393A JP S55160393 A JPS55160393 A JP S55160393A JP 6817779 A JP6817779 A JP 6817779A JP 6817779 A JP6817779 A JP 6817779A JP S55160393 A JPS55160393 A JP S55160393A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- semiconductor memory
- read
- read voltage
- monitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Landscapes
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To make an accurate read possible at any time by equipping an insulating-gate type nonvolatile semiconductor memory with a monitor memory of the same type and the same characteristics. CONSTITUTION:On the substrate of an insulating-gate type nonvolatile semiconductor memory, monitor memory M of the same type and the samd characteristics is formed. Then, once ''0'' and ''1'' are written in the memory, alternation switches S1 and S2 are connected to their 2nd and 3rd contacts to write ''0'' and ''1'' in memory M at the same time. Therefore, when the threshold voltage of the memory changes, the threshold voltage of memory M changes similarly in response to the change. With the memory placed in read mode in the state, read voltage VR' is supplied from the drain of monitor M to the memory via alternation switches. Thus, the read voltage also changes in response to the change in the threshold voltage of the memory, so that an invariably-accurate area can be carried out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6817779A JPS55160393A (en) | 1979-05-31 | 1979-05-31 | Read voltage setting system for semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6817779A JPS55160393A (en) | 1979-05-31 | 1979-05-31 | Read voltage setting system for semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55160393A true JPS55160393A (en) | 1980-12-13 |
| JPS6129075B2 JPS6129075B2 (en) | 1986-07-04 |
Family
ID=13366223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6817779A Granted JPS55160393A (en) | 1979-05-31 | 1979-05-31 | Read voltage setting system for semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55160393A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5936393A (en) * | 1982-08-20 | 1984-02-28 | Mitsubishi Electric Corp | Nonvolatile semiconductor memory device |
| JPS6435798A (en) * | 1987-07-30 | 1989-02-06 | Nec Corp | Non-volatile semiconductor storage device |
| JP2007525778A (en) * | 2003-06-27 | 2007-09-06 | フリースケール セミコンダクター インコーポレイテッド | Variable gate bias for reference transistors in non-volatile memory |
-
1979
- 1979-05-31 JP JP6817779A patent/JPS55160393A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5936393A (en) * | 1982-08-20 | 1984-02-28 | Mitsubishi Electric Corp | Nonvolatile semiconductor memory device |
| JPS6435798A (en) * | 1987-07-30 | 1989-02-06 | Nec Corp | Non-volatile semiconductor storage device |
| JP2007525778A (en) * | 2003-06-27 | 2007-09-06 | フリースケール セミコンダクター インコーポレイテッド | Variable gate bias for reference transistors in non-volatile memory |
| JP4842126B2 (en) * | 2003-06-27 | 2011-12-21 | フリースケール セミコンダクター インコーポレイテッド | Variable gate bias for reference transistors in non-volatile memory |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6129075B2 (en) | 1986-07-04 |
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