[go: up one dir, main page]

JPS55156446A - Bus controller - Google Patents

Bus controller

Info

Publication number
JPS55156446A
JPS55156446A JP6468879A JP6468879A JPS55156446A JP S55156446 A JPS55156446 A JP S55156446A JP 6468879 A JP6468879 A JP 6468879A JP 6468879 A JP6468879 A JP 6468879A JP S55156446 A JPS55156446 A JP S55156446A
Authority
JP
Japan
Prior art keywords
units
transmitting
data transfer
bus controller
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6468879A
Other languages
Japanese (ja)
Other versions
JPS6115461B2 (en
Inventor
Mitsuhiro Ishizaka
Shigeo Nakatsuka
Takane Kakuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6468879A priority Critical patent/JPS55156446A/en
Publication of JPS55156446A publication Critical patent/JPS55156446A/en
Publication of JPS6115461B2 publication Critical patent/JPS6115461B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/3625—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a time dependent access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To make efficient data transfer possible by simultaneously performing data transfer among selected groups of function units in time-division mode. CONSTITUTION:In CPU and a memory unit, transmitting units A0-An-1 and receiving units B0-Bn-1 are connected independently to each other via bus controller 10. Bus controller 10 includes a transmitting register and receiving register, not shown in the figure, corresponding to each transmitting and receving units and a common bus for them. Controller 10 uses this data bus in time-division mode to establish data buses such as data transfer lines P0.1 and P2.n-1 between random units at the same time.
JP6468879A 1979-05-25 1979-05-25 Bus controller Granted JPS55156446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6468879A JPS55156446A (en) 1979-05-25 1979-05-25 Bus controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6468879A JPS55156446A (en) 1979-05-25 1979-05-25 Bus controller

Publications (2)

Publication Number Publication Date
JPS55156446A true JPS55156446A (en) 1980-12-05
JPS6115461B2 JPS6115461B2 (en) 1986-04-24

Family

ID=13265336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6468879A Granted JPS55156446A (en) 1979-05-25 1979-05-25 Bus controller

Country Status (1)

Country Link
JP (1) JPS55156446A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057454A (en) * 1983-06-14 1985-04-03 アプテツク・コンピユ−タ・システムズ・インコ−ポレ−テツド Data transmission system and operation thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057454A (en) * 1983-06-14 1985-04-03 アプテツク・コンピユ−タ・システムズ・インコ−ポレ−テツド Data transmission system and operation thereof

Also Published As

Publication number Publication date
JPS6115461B2 (en) 1986-04-24

Similar Documents

Publication Publication Date Title
CA2050129A1 (en) Dynamic bus arbitration with grant sharing each cycle
EP0147857A3 (en) Parallel data processing system
ES488841A1 (en) Appartus for extending the makro-instruction standard set in a computer.
CA2116826A1 (en) Data Processing System Using a Non-Multiplexed, Asynchronous Address/Data Bus System
JPS54148403A (en) Polling system
JPS55156446A (en) Bus controller
JPS5533213A (en) Information processing system
JPS5723112A (en) Numerical controller
JPS5368940A (en) Information transmission system
JPS56166568A (en) Information processor
JPS5563422A (en) Data transfer system
JPS5310912A (en) Two-way multiplex transmission control system
IE840090L (en) Electronic switching system
JPS566551A (en) Data transfer system in decentralized control system
JPS55150032A (en) Data transfer system
JPS5215241A (en) Bus test control system for data processing system
JPS575143A (en) Communicating method of multimicroprocessor system
JPS6426262A (en) 16 bit microprocessor system
JPS5646351A (en) Serial interface device
JPS51144137A (en) Input/output data control unit
JPS5475941A (en) Control system for memory unit
JPS55116126A (en) Multiplexer channel system
JPS6459446A (en) Information processing system
EP0330110A3 (en) Direct memory access controller
JPS5643850A (en) Intermultiplexer communication control system