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JPS55156424A - Auto clear circuit - Google Patents

Auto clear circuit

Info

Publication number
JPS55156424A
JPS55156424A JP6389879A JP6389879A JPS55156424A JP S55156424 A JPS55156424 A JP S55156424A JP 6389879 A JP6389879 A JP 6389879A JP 6389879 A JP6389879 A JP 6389879A JP S55156424 A JPS55156424 A JP S55156424A
Authority
JP
Japan
Prior art keywords
circuit
terminal
pulse signal
output
signal phi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6389879A
Other languages
Japanese (ja)
Inventor
Isamu Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6389879A priority Critical patent/JPS55156424A/en
Publication of JPS55156424A publication Critical patent/JPS55156424A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied

Landscapes

  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To simplify a circuit by using the boosted voltage of a boosting circuit as the time constant signal of an auto clear circuit. CONSTITUTION:In boosting circuit 1, inverter circuit IN1 receiving fixed pulse signal phi has its output connecting with one terminal of capacitor C1, switching MISFETQ1 is provided between the other terminal of C1 and electric power supply terminal -V, and the series circuit of switching MISFETQ2 and capacitor C2 is further provided between the other terminal of C1 and reference potential OV. Then, FETQ1 and Q2 have their gates controlled by inverted pulse signal phi'' to turn ON FETQ1 with the output of IN1 at a high level of OV or by level-shifted pulse signal phi' to turn ON FETQ2 with the output of IN1 at a low level of (-V).
JP6389879A 1979-05-25 1979-05-25 Auto clear circuit Pending JPS55156424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6389879A JPS55156424A (en) 1979-05-25 1979-05-25 Auto clear circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6389879A JPS55156424A (en) 1979-05-25 1979-05-25 Auto clear circuit

Publications (1)

Publication Number Publication Date
JPS55156424A true JPS55156424A (en) 1980-12-05

Family

ID=13242577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6389879A Pending JPS55156424A (en) 1979-05-25 1979-05-25 Auto clear circuit

Country Status (1)

Country Link
JP (1) JPS55156424A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115030A (en) * 1981-01-09 1982-07-17 Nec Corp Power-on reset circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115030A (en) * 1981-01-09 1982-07-17 Nec Corp Power-on reset circuit

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