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JPS5515526A - Microprogram control circuit - Google Patents

Microprogram control circuit

Info

Publication number
JPS5515526A
JPS5515526A JP8739178A JP8739178A JPS5515526A JP S5515526 A JPS5515526 A JP S5515526A JP 8739178 A JP8739178 A JP 8739178A JP 8739178 A JP8739178 A JP 8739178A JP S5515526 A JPS5515526 A JP S5515526A
Authority
JP
Japan
Prior art keywords
memory unit
associative memory
signal
output signal
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8739178A
Other languages
Japanese (ja)
Inventor
Kuniaki Taga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8739178A priority Critical patent/JPS5515526A/en
Publication of JPS5515526A publication Critical patent/JPS5515526A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To decrease the number of used word on a control memory without causing the lowering of performance by simple hardware by providing an additional associative memory unit for an extesion instruction code.
CONSTITUTION: In the microprogram control circuit, extension instruction code 21 is provided with 2nd associative memory unit 31, which is so set that when 1st associative memory unit 30 is supplied with no output signal, output address information 41 will be obtained by unit 31 without fail corresponding to code 21 as a retrieval signal. Then, setting a random machine-word instruction to instruction register 1 makes it possible to obtain either address signal 40 or 41 of the output signal of 1st or 2nd associative memory unit 30 or 31 via selector circuit 5. Then, control memory address signal 6 of the output signal of circuit 5 indicates the initial address of the microprogram.
COPYRIGHT: (C)1980,JPO&Japio
JP8739178A 1978-07-17 1978-07-17 Microprogram control circuit Pending JPS5515526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8739178A JPS5515526A (en) 1978-07-17 1978-07-17 Microprogram control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8739178A JPS5515526A (en) 1978-07-17 1978-07-17 Microprogram control circuit

Publications (1)

Publication Number Publication Date
JPS5515526A true JPS5515526A (en) 1980-02-02

Family

ID=13913578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8739178A Pending JPS5515526A (en) 1978-07-17 1978-07-17 Microprogram control circuit

Country Status (1)

Country Link
JP (1) JPS5515526A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5727336A (en) * 1980-04-25 1982-02-13 Data General Corp Data processing system
JPS63155327A (en) * 1986-12-19 1988-06-28 Nec Corp Information processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5727336A (en) * 1980-04-25 1982-02-13 Data General Corp Data processing system
JPH0578050B2 (en) * 1980-04-25 1993-10-28 Data General Corp
JPS63155327A (en) * 1986-12-19 1988-06-28 Nec Corp Information processor

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