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JPS5515213A - Manufacturing method for semiconductor device - Google Patents

Manufacturing method for semiconductor device

Info

Publication number
JPS5515213A
JPS5515213A JP8773378A JP8773378A JPS5515213A JP S5515213 A JPS5515213 A JP S5515213A JP 8773378 A JP8773378 A JP 8773378A JP 8773378 A JP8773378 A JP 8773378A JP S5515213 A JPS5515213 A JP S5515213A
Authority
JP
Japan
Prior art keywords
gold
semiconductor
eutectic
silver
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8773378A
Other languages
Japanese (ja)
Inventor
Toshio Tetsuya
Mitsuo Kobayashi
Tsukasa Hattori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8773378A priority Critical patent/JPS5515213A/en
Publication of JPS5515213A publication Critical patent/JPS5515213A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To reduce a use amount of gold and permit mounting of an element in a short time at a low temperature by beforehand forming a gold Si eutecticlayer or a gold silver Si alloy layer on one main face of a semiconductor.
CONSTITUTION: A gold Si eutectic layer or a gold silver alloy layer is formed on a one main face 1 of a semiconductor 11. Further, non-oxide protection metalic film 12 is laminated and covered thereon. On the other hand, a gold eutectic or metal responsive to gold silver alloy or an alloy film 22, for example, gold, silver are beforehand covered on a position to place a semiconductor element. Successively, the semiconductor element is mounted on an element mounting bed, to bond with the element mounting bed by the gold Si eutectic or gold silver alloy contacted therewith. Whereby the gold amount to be used can be considerably reduced compared with for a gold priform body, the heating temperature in mounting the element be restricted and the manufacture be established in a short time.
COPYRIGHT: (C)1980,JPO&Japio
JP8773378A 1978-07-20 1978-07-20 Manufacturing method for semiconductor device Pending JPS5515213A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8773378A JPS5515213A (en) 1978-07-20 1978-07-20 Manufacturing method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8773378A JPS5515213A (en) 1978-07-20 1978-07-20 Manufacturing method for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5515213A true JPS5515213A (en) 1980-02-02

Family

ID=13923115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8773378A Pending JPS5515213A (en) 1978-07-20 1978-07-20 Manufacturing method for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5515213A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS509148A (en) * 1973-05-30 1975-01-30

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS509148A (en) * 1973-05-30 1975-01-30

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