JPS55149536A - Logic circuit - Google Patents

Abstract

PURPOSE:To avoid the malfunction of logic section, by writing in the asynchronous signal to the first logic section with the first clock signal and writing in the first clock signal to the second logic section with the second clock signal delayed. CONSTITUTION:The asynchronous signal input to the terminal 1 is written in FF5 via the gates 6, 7 with the clock signal phi1 from the clock input terminal. The clock signal phi1 is delayed at th delay circuit 10 and fed to FETs Q1, Q2 as the clock signals phi1' and phi1''. FETs Q1, Q2 write in the output signal of FF5 to the latch circuits 3, 4 with the clock signals phi1' and phi1''. Accordingly, the logic circuit is not malfunctioned with the delay circuit 10.