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JPS55143047A - Insulating separation method for semiconductor device - Google Patents

Insulating separation method for semiconductor device

Info

Publication number
JPS55143047A
JPS55143047A JP5123279A JP5123279A JPS55143047A JP S55143047 A JPS55143047 A JP S55143047A JP 5123279 A JP5123279 A JP 5123279A JP 5123279 A JP5123279 A JP 5123279A JP S55143047 A JPS55143047 A JP S55143047A
Authority
JP
Japan
Prior art keywords
film
region
channel
films
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5123279A
Other languages
Japanese (ja)
Other versions
JPS6228579B2 (en
Inventor
Nobuhiro Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5123279A priority Critical patent/JPS55143047A/en
Publication of JPS55143047A publication Critical patent/JPS55143047A/en
Publication of JPS6228579B2 publication Critical patent/JPS6228579B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To surely separate a channel stopper region from a source and drain region produced afterwards, by providing a polycrystalline Si layer on a channel region and causing an oxide field film to extend into the Si layer when producing the oxide film on the stopper region. CONSTITUTION:An SiO2 film 2, a polycrystalline Si film 3, an Si3N4 film 4 are laminated on a p-type Si substrate 1. These films are left on only a channel region by photoetching. A p-type channel stopper region 5 is produced by diffusion in the substrate 1 beside the channel region while the photoetched films are used as a mask. Thermal oxidation is caused under an atmosphere of steam so that a thick oxide field film 6 is made on the stopper region 5 and the front end of the film 6 extends into the polycrystalline film 3. After that, the films 4, 3, 2 are all removed. A contacted opening is made in the channel region. A thin SiO2 gate film 8 is provided in the opening. A gate electrode 9 is provided on the film 8 in the opening. An n-type source and drain region 10 is produced by diffusion while the electrode 9 is used as a mask.
JP5123279A 1979-04-25 1979-04-25 Insulating separation method for semiconductor device Granted JPS55143047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5123279A JPS55143047A (en) 1979-04-25 1979-04-25 Insulating separation method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5123279A JPS55143047A (en) 1979-04-25 1979-04-25 Insulating separation method for semiconductor device

Publications (2)

Publication Number Publication Date
JPS55143047A true JPS55143047A (en) 1980-11-08
JPS6228579B2 JPS6228579B2 (en) 1987-06-22

Family

ID=12881191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5123279A Granted JPS55143047A (en) 1979-04-25 1979-04-25 Insulating separation method for semiconductor device

Country Status (1)

Country Link
JP (1) JPS55143047A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5972740A (en) * 1982-10-19 1984-04-24 Nec Corp Semiconductor integrated circuit device and manufacture thereof
JPS6083348A (en) * 1983-10-14 1985-05-11 Hitachi Ltd Semiconductor integrated circuit device
US4968640A (en) * 1987-02-10 1990-11-06 Industrial Technology Research Institute Isolation structures for integrated circuits
JPH04116932A (en) * 1990-09-07 1992-04-17 Mitsubishi Electric Corp Semiconductor device
US5348910A (en) * 1991-12-24 1994-09-20 Seiko Epson Corporation Method of manufacturing a semiconductor device and the product thereby

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51142982A (en) * 1975-05-05 1976-12-08 Intel Corp Method of producing single crystal silicon ic

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51142982A (en) * 1975-05-05 1976-12-08 Intel Corp Method of producing single crystal silicon ic

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5972740A (en) * 1982-10-19 1984-04-24 Nec Corp Semiconductor integrated circuit device and manufacture thereof
JPS6083348A (en) * 1983-10-14 1985-05-11 Hitachi Ltd Semiconductor integrated circuit device
US4968640A (en) * 1987-02-10 1990-11-06 Industrial Technology Research Institute Isolation structures for integrated circuits
JPH04116932A (en) * 1990-09-07 1992-04-17 Mitsubishi Electric Corp Semiconductor device
US5348910A (en) * 1991-12-24 1994-09-20 Seiko Epson Corporation Method of manufacturing a semiconductor device and the product thereby

Also Published As

Publication number Publication date
JPS6228579B2 (en) 1987-06-22

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