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JPS55138867A - Memory device - Google Patents

Memory device

Info

Publication number
JPS55138867A
JPS55138867A JP4684679A JP4684679A JPS55138867A JP S55138867 A JPS55138867 A JP S55138867A JP 4684679 A JP4684679 A JP 4684679A JP 4684679 A JP4684679 A JP 4684679A JP S55138867 A JPS55138867 A JP S55138867A
Authority
JP
Japan
Prior art keywords
layers
substrate
type
conducting
ohmic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4684679A
Other languages
Japanese (ja)
Other versions
JPS6410104B2 (en
Inventor
Koji Eguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4684679A priority Critical patent/JPS55138867A/en
Publication of JPS55138867A publication Critical patent/JPS55138867A/en
Publication of JPS6410104B2 publication Critical patent/JPS6410104B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H10B99/22—Subject matter not provided for in other groups of this subclass including field-effect components

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To highly integrate a memory device in high packing density by conducting the source region of a one conducting type channel insulated gate FET with a reverse conducting well formed on the substrate or in one conducting type substrate to supply a current from the lower portion thereto. CONSTITUTION:N<+>-type diffused layers 203, 204 are formed between P<+>-type diffused layers 201 and 202, both layers are connected with aluminum electrodes 205 and 206, respectively to ohmic connect between the substrate 207 and the layers 201, 202. The bottom surface 208 of the substrate 207 is conducted with a VCC power supply. Thus, the layers 201, 202 are ohmic connected through the layers 203, 204 directly to an n-type substrate so as to omit the P<+>-type diffused layer wire connected to the VCC power supply and to reduce the memory cell area.
JP4684679A 1979-04-17 1979-04-17 Memory device Granted JPS55138867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4684679A JPS55138867A (en) 1979-04-17 1979-04-17 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4684679A JPS55138867A (en) 1979-04-17 1979-04-17 Memory device

Publications (2)

Publication Number Publication Date
JPS55138867A true JPS55138867A (en) 1980-10-30
JPS6410104B2 JPS6410104B2 (en) 1989-02-21

Family

ID=12758696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4684679A Granted JPS55138867A (en) 1979-04-17 1979-04-17 Memory device

Country Status (1)

Country Link
JP (1) JPS55138867A (en)

Also Published As

Publication number Publication date
JPS6410104B2 (en) 1989-02-21

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