JPS55137748A - Packet transmission and receiving system - Google Patents
Packet transmission and receiving systemInfo
- Publication number
- JPS55137748A JPS55137748A JP4641679A JP4641679A JPS55137748A JP S55137748 A JPS55137748 A JP S55137748A JP 4641679 A JP4641679 A JP 4641679A JP 4641679 A JP4641679 A JP 4641679A JP S55137748 A JPS55137748 A JP S55137748A
- Authority
- JP
- Japan
- Prior art keywords
- packet
- destination
- buffer
- storage memory
- transmitted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 title abstract 2
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
PURPOSE:To shorten the transmission delay time and improve the use efficiency of a main storage memory, by providing a time division switch and a buffer for packet corresponding to a traffic to transmit and receive directly packets between lines. CONSTITUTION:When arrival of a packet transmitted through incoming line LN1 is detected, the packet is input to a buffer for packet storage by the closing control of time division switch PHSW. Meanwhile, destination translating circuit KNTLR compares the destination of the packet with routing information of routing information storage memory RIDX for destination translation to decide outgoing line LN2, and contents of buffer PBF are sent to prescribed outgoing line LN2 by the control of control circuit SHWC, thus repeating the packet. Then, the packet transmitted to or from its own exchange is transmitted to or received by main storage memory MM through interface control part IFC and data channel CH.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54046416A JPS5854701B2 (en) | 1979-04-16 | 1979-04-16 | Packet transmission/reception method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54046416A JPS5854701B2 (en) | 1979-04-16 | 1979-04-16 | Packet transmission/reception method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55137748A true JPS55137748A (en) | 1980-10-27 |
JPS5854701B2 JPS5854701B2 (en) | 1983-12-06 |
Family
ID=12746536
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54046416A Expired JPS5854701B2 (en) | 1979-04-16 | 1979-04-16 | Packet transmission/reception method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5854701B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6053017U (en) * | 1983-09-21 | 1985-04-13 | 横河電機株式会社 | measuring device |
JPS62200443A (en) * | 1986-02-28 | 1987-09-04 | Canon Inc | Electronic equipment |
-
1979
- 1979-04-16 JP JP54046416A patent/JPS5854701B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5854701B2 (en) | 1983-12-06 |
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