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JPS55135930A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS55135930A
JPS55135930A JP4374279A JP4374279A JPS55135930A JP S55135930 A JPS55135930 A JP S55135930A JP 4374279 A JP4374279 A JP 4374279A JP 4374279 A JP4374279 A JP 4374279A JP S55135930 A JPS55135930 A JP S55135930A
Authority
JP
Japan
Prior art keywords
data transfer
module
transfer
data
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4374279A
Other languages
Japanese (ja)
Other versions
JPS6214869B2 (en
Inventor
Fumio Nishimura
Norio Aihara
Takashi Nagashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4374279A priority Critical patent/JPS55135930A/en
Publication of JPS55135930A publication Critical patent/JPS55135930A/en
Publication of JPS6214869B2 publication Critical patent/JPS6214869B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Advance Control (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE: To reduce a burden of CPU due to a data transfer and to elevate both the transfer rate and the transfer efficiency, by carrying out through the transfer module in case of transferring a data between each module such as CPU connected with a bus, the main memory, the input/output device, etc.
CONSTITUTION: A data transfer module 4 which has received an input/output instruction from CPU2 analyses selection of the input/output device 3 relating to the kind of operation and the data transfer by command analysis part. And the operation circuit 13 performs an optional operation indicated by the output, to the analysis part 12, and the output of this circuit 13 is selected 14 in accordance with the instruction from the analysis part 13 and is returned to the bus. Resulting from the foregoing, it is possible to reduce a burden of CPU2 relating to the data transfer and to elevate both the transfer rate and the data transfer efficiency of the system, by transferring a data between each module connected to the bus, through the module 4.
COPYRIGHT: (C)1980,JPO&Japio
JP4374279A 1979-04-11 1979-04-11 Data transfer system Granted JPS55135930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4374279A JPS55135930A (en) 1979-04-11 1979-04-11 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4374279A JPS55135930A (en) 1979-04-11 1979-04-11 Data transfer system

Publications (2)

Publication Number Publication Date
JPS55135930A true JPS55135930A (en) 1980-10-23
JPS6214869B2 JPS6214869B2 (en) 1987-04-04

Family

ID=12672213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4374279A Granted JPS55135930A (en) 1979-04-11 1979-04-11 Data transfer system

Country Status (1)

Country Link
JP (1) JPS55135930A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57132229A (en) * 1981-02-09 1982-08-16 Mitsubishi Electric Corp Direct memory access controller

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5074350A (en) * 1973-10-31 1975-06-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5074350A (en) * 1973-10-31 1975-06-19

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57132229A (en) * 1981-02-09 1982-08-16 Mitsubishi Electric Corp Direct memory access controller

Also Published As

Publication number Publication date
JPS6214869B2 (en) 1987-04-04

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