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JPS55124846A - Microprogram control system - Google Patents

Microprogram control system

Info

Publication number
JPS55124846A
JPS55124846A JP3111479A JP3111479A JPS55124846A JP S55124846 A JPS55124846 A JP S55124846A JP 3111479 A JP3111479 A JP 3111479A JP 3111479 A JP3111479 A JP 3111479A JP S55124846 A JPS55124846 A JP S55124846A
Authority
JP
Japan
Prior art keywords
bit
interruption
microprogram
program level
under execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3111479A
Other languages
Japanese (ja)
Other versions
JPS6218937B2 (en
Inventor
Masakazu Okada
Hitoshi Fushimi
Seiichi Yasumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3111479A priority Critical patent/JPS55124846A/en
Publication of JPS55124846A publication Critical patent/JPS55124846A/en
Publication of JPS6218937B2 publication Critical patent/JPS6218937B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To enable interruption processing simply in high speed, by providing mask bit every one instruction of microprogram.
CONSTITUTION: The program level under execution at present is written in the lower 2-bit of the level register 10. The comparator 8 compares the program level under execution at present with the program level for interruption processing to discriminate whether or not the interruption request is received. The comparator 8 is of 3-bit construction, the most significant bit of interruption factor is always made to "0", and the most significant bit of input of the register 10 is the mask bit provided at every one instruction of microprogram. When the mask bit is "1", since the program level under execution is high, the interruption processing is inhibited. The discrimination of interruption can simply be made every one step of microprogram.
COPYRIGHT: (C)1980,JPO&Japio
JP3111479A 1979-03-19 1979-03-19 Microprogram control system Granted JPS55124846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3111479A JPS55124846A (en) 1979-03-19 1979-03-19 Microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3111479A JPS55124846A (en) 1979-03-19 1979-03-19 Microprogram control system

Publications (2)

Publication Number Publication Date
JPS55124846A true JPS55124846A (en) 1980-09-26
JPS6218937B2 JPS6218937B2 (en) 1987-04-25

Family

ID=12322366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3111479A Granted JPS55124846A (en) 1979-03-19 1979-03-19 Microprogram control system

Country Status (1)

Country Link
JP (1) JPS55124846A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5999553A (en) * 1982-11-29 1984-06-08 Nec Corp Interruption control system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63116942U (en) * 1987-01-19 1988-07-28

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5999553A (en) * 1982-11-29 1984-06-08 Nec Corp Interruption control system

Also Published As

Publication number Publication date
JPS6218937B2 (en) 1987-04-25

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