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JPS55122285A - Substitute control system in buffer memory - Google Patents

Substitute control system in buffer memory

Info

Publication number
JPS55122285A
JPS55122285A JP2745879A JP2745879A JPS55122285A JP S55122285 A JPS55122285 A JP S55122285A JP 2745879 A JP2745879 A JP 2745879A JP 2745879 A JP2745879 A JP 2745879A JP S55122285 A JPS55122285 A JP S55122285A
Authority
JP
Japan
Prior art keywords
circuit
block area
selects
block
update
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2745879A
Other languages
Japanese (ja)
Inventor
Akiyoshi Kajiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2745879A priority Critical patent/JPS55122285A/en
Publication of JPS55122285A publication Critical patent/JPS55122285A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To make it possible to reduce considerably the number of bits for block substitute control, by causing a substitute order display memory to have update order bit groups by the number of sets and by causing respective bits to correspond to set addresses.
CONSTITUTION: Update block area address generation circuit 1 receives the block agreement signal from a tag part to generate an update block area address. Input circuit 2 selects an update order bit and generates write data. Substitute order display memory 3 has update order display bit groups consisting of update order display bits A0WC3 by the number of sets and selects one update order bit group corresponding to the set address. The output memory 3 is inputted to output circuit 5 through delete circuit 4, and circuit 5 selects and outputs the block area where oldest data should be stored. Selection circuit 6 selects an idle block area as a write block area when the idle block area exists, and circuit 6 selects the oldest block area as a write block when the idle block are does not exist.
COPYRIGHT: (C)1980,JPO&Japio
JP2745879A 1979-03-09 1979-03-09 Substitute control system in buffer memory Pending JPS55122285A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2745879A JPS55122285A (en) 1979-03-09 1979-03-09 Substitute control system in buffer memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2745879A JPS55122285A (en) 1979-03-09 1979-03-09 Substitute control system in buffer memory

Publications (1)

Publication Number Publication Date
JPS55122285A true JPS55122285A (en) 1980-09-19

Family

ID=12221667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2745879A Pending JPS55122285A (en) 1979-03-09 1979-03-09 Substitute control system in buffer memory

Country Status (1)

Country Link
JP (1) JPS55122285A (en)

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