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JPS55118248A - Timing extracting circuit - Google Patents

Timing extracting circuit

Info

Publication number
JPS55118248A
JPS55118248A JP2576679A JP2576679A JPS55118248A JP S55118248 A JPS55118248 A JP S55118248A JP 2576679 A JP2576679 A JP 2576679A JP 2576679 A JP2576679 A JP 2576679A JP S55118248 A JPS55118248 A JP S55118248A
Authority
JP
Japan
Prior art keywords
signal
signals
circuit
timing
threshold value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2576679A
Other languages
Japanese (ja)
Inventor
Fuji Kanemasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2576679A priority Critical patent/JPS55118248A/en
Publication of JPS55118248A publication Critical patent/JPS55118248A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To establish the timing extracting circuit for bipolar transmission, in which only the correct timing signal is extracted among the timing information obtained from the conversion point of the signal slicing the input signal with a given threshold value. CONSTITUTION:The input signal (a) is made to the signal (b) with the delay circuit 2 having pulse repetition of period for bipolar signal. The signals (a) and (b) are fed to the threshold value circuit 3, 4 having the threshold values TH1, -TH1 and converted into the signals (c), (d), (e). The control circuit 5 produces the signals (g), (h), (i) from the signal (c), (d) and (e) respectively and selectively the signals (g) or (h) is outputted based on the signal (i). This output is the signal (J) and is correct timing signal having a multiple of baud rate period for the pulse distance. This signal J is used for the phase control circuit 6.
JP2576679A 1979-03-06 1979-03-06 Timing extracting circuit Pending JPS55118248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2576679A JPS55118248A (en) 1979-03-06 1979-03-06 Timing extracting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2576679A JPS55118248A (en) 1979-03-06 1979-03-06 Timing extracting circuit

Publications (1)

Publication Number Publication Date
JPS55118248A true JPS55118248A (en) 1980-09-11

Family

ID=12174953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2576679A Pending JPS55118248A (en) 1979-03-06 1979-03-06 Timing extracting circuit

Country Status (1)

Country Link
JP (1) JPS55118248A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4700357A (en) * 1984-11-22 1987-10-13 Siemens Aktiengesellschaft Synchronizing stage for the acquisition of a synchronizing signal having low jitter from a biternary data sequence
JPH0354934A (en) * 1989-07-24 1991-03-08 Canon Inc Phase locked loop circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4700357A (en) * 1984-11-22 1987-10-13 Siemens Aktiengesellschaft Synchronizing stage for the acquisition of a synchronizing signal having low jitter from a biternary data sequence
JPH0354934A (en) * 1989-07-24 1991-03-08 Canon Inc Phase locked loop circuit

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