JPS55117330A - Adaptive differential modulation coding/decoding device - Google Patents
Adaptive differential modulation coding/decoding deviceInfo
- Publication number
- JPS55117330A JPS55117330A JP2477079A JP2477079A JPS55117330A JP S55117330 A JPS55117330 A JP S55117330A JP 2477079 A JP2477079 A JP 2477079A JP 2477079 A JP2477079 A JP 2477079A JP S55117330 A JPS55117330 A JP S55117330A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- step size
- code
- delivered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/02—Delta modulation, i.e. one-bit differential modulation
- H03M3/022—Delta modulation, i.e. one-bit differential modulation with adaptable step size, e.g. adaptive delta modulation [ADM]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Abstract
PURPOSE:To realize the adaptive step size by varying the number of the high-speed integrating pulses in accordance with the quantized step size and via the digital circuit, thus omitting the circuit requiring the complicated accuracy and then facilitating the LSI formation. CONSTITUTION:Adaptive delta modulation code 108 is delivered from sampling/ quantizing circuit 107 in response to the rise of sampling clock pulse 114 applied to terminal 106. Then code 108 is applied to step size deciding circuit 109, and thus the step size is decided based on the past code series to deliver signal 110. Signal 110 is then applied to pulse number control circuit 201 of integrated pulse generator circuit 211, and high-speed integrated pulse number control signal 202 is delivered to the output. At the same time, high-speed clock pulse 204 is applied to terminal 203, and the logic sum is secured through AND gate 205 to signal 202. Then clock signal 206 is applied to gates 207 and 208 along with code 108, and high-speed integrated pulses 209 and 210 are delivered to the output and then applied to integrating circuit 113. Thus the fixed amount of charge and discharge is carried out in response to pulses 209 and 210.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2477079A JPS55117330A (en) | 1979-03-02 | 1979-03-02 | Adaptive differential modulation coding/decoding device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2477079A JPS55117330A (en) | 1979-03-02 | 1979-03-02 | Adaptive differential modulation coding/decoding device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55117330A true JPS55117330A (en) | 1980-09-09 |
Family
ID=12147390
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2477079A Pending JPS55117330A (en) | 1979-03-02 | 1979-03-02 | Adaptive differential modulation coding/decoding device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55117330A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62110327A (en) * | 1985-11-08 | 1987-05-21 | Matsushita Electric Ind Co Ltd | Adaptive delta modulator-demodulator |
-
1979
- 1979-03-02 JP JP2477079A patent/JPS55117330A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62110327A (en) * | 1985-11-08 | 1987-05-21 | Matsushita Electric Ind Co Ltd | Adaptive delta modulator-demodulator |
JPH0362326B2 (en) * | 1985-11-08 | 1991-09-25 | Matsushita Electric Ind Co Ltd |
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