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JPS55115351A - Ic stem - Google Patents

Ic stem

Info

Publication number
JPS55115351A
JPS55115351A JP2239679A JP2239679A JPS55115351A JP S55115351 A JPS55115351 A JP S55115351A JP 2239679 A JP2239679 A JP 2239679A JP 2239679 A JP2239679 A JP 2239679A JP S55115351 A JPS55115351 A JP S55115351A
Authority
JP
Japan
Prior art keywords
pins
insulating substrate
stem
concave
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2239679A
Other languages
Japanese (ja)
Inventor
Akira Shimohashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2239679A priority Critical patent/JPS55115351A/en
Publication of JPS55115351A publication Critical patent/JPS55115351A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To obtain a small-sized stem with greater mechanical intensity and high performance by laminating one insulating substrate, on which a part of conductors are formed, on the other insulating substrate, on which the remains of said conductors are provided, so that the former is projected from the latter outwards and by providing insulator between rows of the outer end pins.
CONSTITUTION: The concave 2 for installing the IC chip 3 is formed inside of the connecting conductor 4 on the insulating substrate 9 and the connecting pins 6 are provided to both outer ends of the conductor 4. The escape hole 11 for the wiring, which is greater than the concave 2, is formed in the insulating substrate 10 that is laminated on the said one 9, both the end faces of the substrate 10, in which the connecting pins 13 for the connecting conductor 12 are arranged, are projected from the substrate 9 outwards. The connection to the chip 3 is performed, the cover 15 with the concave 16 is placed on the element, the insulator 14 is put into the space between the rows of pins 6, 13 to make the element one body. In this way, a little space can be expanded in the direction of width of the IC stem for an increase of the number of pins without a change of the dimension in the lengthwise direction of the stem, a small-sized device with a sufficient mechanical intensity can be obtained.
COPYRIGHT: (C)1980,JPO&Japio
JP2239679A 1979-02-26 1979-02-26 Ic stem Pending JPS55115351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2239679A JPS55115351A (en) 1979-02-26 1979-02-26 Ic stem

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2239679A JPS55115351A (en) 1979-02-26 1979-02-26 Ic stem

Publications (1)

Publication Number Publication Date
JPS55115351A true JPS55115351A (en) 1980-09-05

Family

ID=12081491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2239679A Pending JPS55115351A (en) 1979-02-26 1979-02-26 Ic stem

Country Status (1)

Country Link
JP (1) JPS55115351A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4618879A (en) * 1983-04-20 1986-10-21 Fujitsu Limited Semiconductor device having adjacent bonding wires extending at different angles
US4638348A (en) * 1982-08-10 1987-01-20 Brown David F Semiconductor chip carrier
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
US5818108A (en) * 1993-06-08 1998-10-06 Alcatel N.V. High-density, highly reliable integrated circuit assembly

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4638348A (en) * 1982-08-10 1987-01-20 Brown David F Semiconductor chip carrier
AT398254B (en) * 1982-08-10 1994-11-25 Dowty Electronic Components CHIP CARRIERS AND ARRANGEMENT OF SUCH CHIP CARRIERS
US4618879A (en) * 1983-04-20 1986-10-21 Fujitsu Limited Semiconductor device having adjacent bonding wires extending at different angles
US5818108A (en) * 1993-06-08 1998-10-06 Alcatel N.V. High-density, highly reliable integrated circuit assembly
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers

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