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JPS55100762A - Pll stereo decoder - Google Patents

Pll stereo decoder

Info

Publication number
JPS55100762A
JPS55100762A JP778379A JP778379A JPS55100762A JP S55100762 A JPS55100762 A JP S55100762A JP 778379 A JP778379 A JP 778379A JP 778379 A JP778379 A JP 778379A JP S55100762 A JPS55100762 A JP S55100762A
Authority
JP
Japan
Prior art keywords
stereo
control oscillator
pll
circuit
phi2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP778379A
Other languages
Japanese (ja)
Inventor
Hisao Kuwabara
Asahiro Masaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP778379A priority Critical patent/JPS55100762A/en
Publication of JPS55100762A publication Critical patent/JPS55100762A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
    • H04H40/45—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
    • H04H40/81—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving for stereo-monaural switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/22—Homodyne or synchrodyne circuits
    • H03D1/2209—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders
    • H03D1/2236—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders using a phase locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Stereo-Broadcasting Methods (AREA)

Abstract

PURPOSE:To prevent error display when a control oscillator is stopped by providing a responding circuit which operates, interlocking with a switch which stops selectively the operation of the voltage control oscillator included in a phase-synchronous loop, to let a stereo indicator go off. CONSTITUTION:A pilot signal included in a stereo composite signal inputted to stereo decoder circuit 11 is detected, frequency-multiplied and applied to PLL to generate a switching signal for stereo demodulation. When this pilot signal exists, lamp driver circuit DRIV is driven to make stereo indicator IND come on. The traveling terminal of VCO stop switch S1 stopping selectively the operation of voltage control oscillator VCO included in the loop of this PLL is connected to integrating circuit INTE and the base of transistor Q1 grounding the output of 2nd phase comparator phi2, so that error display when the output of comparator phi2 is at a fixed level or below will be inhibited.
JP778379A 1979-01-26 1979-01-26 Pll stereo decoder Pending JPS55100762A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP778379A JPS55100762A (en) 1979-01-26 1979-01-26 Pll stereo decoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP778379A JPS55100762A (en) 1979-01-26 1979-01-26 Pll stereo decoder

Publications (1)

Publication Number Publication Date
JPS55100762A true JPS55100762A (en) 1980-07-31

Family

ID=11675265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP778379A Pending JPS55100762A (en) 1979-01-26 1979-01-26 Pll stereo decoder

Country Status (1)

Country Link
JP (1) JPS55100762A (en)

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