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JPS5492141A - Interface control system - Google Patents

Interface control system

Info

Publication number
JPS5492141A
JPS5492141A JP16045377A JP16045377A JPS5492141A JP S5492141 A JPS5492141 A JP S5492141A JP 16045377 A JP16045377 A JP 16045377A JP 16045377 A JP16045377 A JP 16045377A JP S5492141 A JPS5492141 A JP S5492141A
Authority
JP
Japan
Prior art keywords
signal lines
terminal
receiver
host computer
connection interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16045377A
Other languages
Japanese (ja)
Inventor
Minami Kikawada
Hisashi Sukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16045377A priority Critical patent/JPS5492141A/en
Publication of JPS5492141A publication Critical patent/JPS5492141A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enable a system to operate even if a terminal fed with no power exists, and to make it possible to connect or disconnect a power supply to or from any terminal by providing interruption signal lines between a host computer and several terminals.
CONSTITUTION: Host computer 1 is connected to terminals 2-1 to 2-7 via corresponding interruption signal lines 4-1 to 4-7. In addition, the data processing system includes multiple-connection interface signal lines 3-1 to 3-8. Terminal part 2i (i=1 to 7) consists of receiver 5, control register 6, sense register 7, driver 8, bus change- over circuit 9, etc., and when the power supply is put to work, circuit 9 connects driver 8 to multiple-connection interface signal line 3-(i+1). Further, the input of receiver 5 is connected invariably to prior-stage signal line 3-i regardless of the power feeding state or change-over 9 state.
COPYRIGHT: (C)1979,JPO&Japio
JP16045377A 1977-12-29 1977-12-29 Interface control system Pending JPS5492141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16045377A JPS5492141A (en) 1977-12-29 1977-12-29 Interface control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16045377A JPS5492141A (en) 1977-12-29 1977-12-29 Interface control system

Publications (1)

Publication Number Publication Date
JPS5492141A true JPS5492141A (en) 1979-07-21

Family

ID=15715254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16045377A Pending JPS5492141A (en) 1977-12-29 1977-12-29 Interface control system

Country Status (1)

Country Link
JP (1) JPS5492141A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694815A (en) * 1979-12-28 1981-07-31 Matsushita Electric Ind Co Ltd Elastic surface wave device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694815A (en) * 1979-12-28 1981-07-31 Matsushita Electric Ind Co Ltd Elastic surface wave device

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