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JPS5489761A - counter synchronizing circuit - Google Patents

counter synchronizing circuit

Info

Publication number
JPS5489761A
JPS5489761A JP15992777A JP15992777A JPS5489761A JP S5489761 A JPS5489761 A JP S5489761A JP 15992777 A JP15992777 A JP 15992777A JP 15992777 A JP15992777 A JP 15992777A JP S5489761 A JPS5489761 A JP S5489761A
Authority
JP
Japan
Prior art keywords
digit
circuit
counter
code transmitter
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15992777A
Other languages
Japanese (ja)
Other versions
JPS6046760B2 (en
Inventor
Minoru Tomonaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP52159927A priority Critical patent/JPS6046760B2/en
Publication of JPS5489761A publication Critical patent/JPS5489761A/en
Publication of JPS6046760B2 publication Critical patent/JPS6046760B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Arrangements For Transmission Of Measured Signals (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To eliminate time deviations between digit signals of a counter and achieve the reduction in power consumption by performing dynamic operation during the time when synchronizing of the digit signals of the couter is taken by the digit scan signals of a code transmitter.
CONSTITUTION: When the digit scanning signal for calling is entered from a code transmitter and 1 signal is produced from an exclusive-OR circuit 126, an oscillator circuit 13 performs oscillation operation, subsequently shifting the digit signals T1 thru T4 of an IC counter 11. When at this time the digit which has a call from the code transmitter and the digit output of the IC counter 11 coincide, the 1 signal is outputted from the OR circuit 124 through AND circuit 120 or 121, 122, 123, due to which the exclusive-OR circuit 126 becomes 0 and the transmission of the oscillator circuit 13 stops. As a result, the IC counter 11 stops while outputting the BCD data of the digit which ahd call request from the code transmitter and this turns out that the perfect synchronization may be taken.
COPYRIGHT: (C)1979,JPO&Japio
JP52159927A 1977-12-27 1977-12-27 counter synchronization circuit Expired JPS6046760B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52159927A JPS6046760B2 (en) 1977-12-27 1977-12-27 counter synchronization circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52159927A JPS6046760B2 (en) 1977-12-27 1977-12-27 counter synchronization circuit

Publications (2)

Publication Number Publication Date
JPS5489761A true JPS5489761A (en) 1979-07-17
JPS6046760B2 JPS6046760B2 (en) 1985-10-17

Family

ID=15704181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52159927A Expired JPS6046760B2 (en) 1977-12-27 1977-12-27 counter synchronization circuit

Country Status (1)

Country Link
JP (1) JPS6046760B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012125397A2 (en) 2011-03-11 2012-09-20 Kraft Foods Global Brands Llc System and method of forming multilayer confectionery

Also Published As

Publication number Publication date
JPS6046760B2 (en) 1985-10-17

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