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JPS5489428A - Pattern generator - Google Patents

Pattern generator

Info

Publication number
JPS5489428A
JPS5489428A JP15764577A JP15764577A JPS5489428A JP S5489428 A JPS5489428 A JP S5489428A JP 15764577 A JP15764577 A JP 15764577A JP 15764577 A JP15764577 A JP 15764577A JP S5489428 A JPS5489428 A JP S5489428A
Authority
JP
Japan
Prior art keywords
rom
register
counter
pattern data
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15764577A
Other languages
Japanese (ja)
Other versions
JPS6053875B2 (en
Inventor
Masashi Deguchi
Hiroshi Izumi
Yoshitaka Shimamura
Sumio Ozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15764577A priority Critical patent/JPS6053875B2/en
Publication of JPS5489428A publication Critical patent/JPS5489428A/en
Publication of JPS6053875B2 publication Critical patent/JPS6053875B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the capacity of a memory and generate easily arbitrary patterns different in a size by combining a general-purpose P-ROM, a shift register and a counter circuit.
CONSTITUTION: The storage start address of character and symbol patterns is set in pre-set counter 2, and pattern data from P-ROM 1 addressed by this address enters output shift register 3 which is shifted successively according to external clock signals. The output of register 3 outputs data of every dot of a pattern through output buffer 4. Counter 5 counts the number of shift times of register 3 and issues a signal by which contents of counter 2 is counted up by +1, and P-ROM 1 outputs pattern data of the next address to register 3. As a result, pattern data is stored in P-ROM so that pattern data cannot have space surplus as shown in the figure, and therefore, the capacity of the memory can be reduced, and special patterns can be generated.
COPYRIGHT: (C)1979,JPO&Japio
JP15764577A 1977-12-27 1977-12-27 pattern generator Expired JPS6053875B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15764577A JPS6053875B2 (en) 1977-12-27 1977-12-27 pattern generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15764577A JPS6053875B2 (en) 1977-12-27 1977-12-27 pattern generator

Publications (2)

Publication Number Publication Date
JPS5489428A true JPS5489428A (en) 1979-07-16
JPS6053875B2 JPS6053875B2 (en) 1985-11-27

Family

ID=15654243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15764577A Expired JPS6053875B2 (en) 1977-12-27 1977-12-27 pattern generator

Country Status (1)

Country Link
JP (1) JPS6053875B2 (en)

Also Published As

Publication number Publication date
JPS6053875B2 (en) 1985-11-27

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