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JPS5470089A - Effective value detection circuit - Google Patents

Effective value detection circuit

Info

Publication number
JPS5470089A
JPS5470089A JP13697677A JP13697677A JPS5470089A JP S5470089 A JPS5470089 A JP S5470089A JP 13697677 A JP13697677 A JP 13697677A JP 13697677 A JP13697677 A JP 13697677A JP S5470089 A JPS5470089 A JP S5470089A
Authority
JP
Japan
Prior art keywords
supplied
effective value
adder
fixed period
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13697677A
Other languages
Japanese (ja)
Inventor
Tadashi Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13697677A priority Critical patent/JPS5470089A/en
Publication of JPS5470089A publication Critical patent/JPS5470089A/en
Pending legal-status Critical Current

Links

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  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE: To detect effective value outputs readily and satisfactorily by subtracting input signals from added value with a delay of a fixed period.
CONSTITUTION: The continuously changing signals having been supplied to input terminal IN1 are supplied to an adder S1 consisting of a resistance R1, capacitor C1 and operational amplifier A1 and are thereby added. They are also delayed for a fixed period and are made to antiphase by way of a delay circuit D1 and inversion amplifier A2 and are supplied to the adder S1. Then the output from the adder circuit S1 becomes the one in which the integrated value of the signal components having delayed the input signals for a fixed period is subtracted from the added value, thus the continuous effective value output in the strict sence of not having any frequency characteristic is surely derived out from output end OUT1.
COPYRIGHT: (C)1979,JPO&Japio
JP13697677A 1977-11-15 1977-11-15 Effective value detection circuit Pending JPS5470089A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13697677A JPS5470089A (en) 1977-11-15 1977-11-15 Effective value detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13697677A JPS5470089A (en) 1977-11-15 1977-11-15 Effective value detection circuit

Publications (1)

Publication Number Publication Date
JPS5470089A true JPS5470089A (en) 1979-06-05

Family

ID=15187858

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13697677A Pending JPS5470089A (en) 1977-11-15 1977-11-15 Effective value detection circuit

Country Status (1)

Country Link
JP (1) JPS5470089A (en)

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