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JPS5460508A - Initial program loading system - Google Patents

Initial program loading system

Info

Publication number
JPS5460508A
JPS5460508A JP12685777A JP12685777A JPS5460508A JP S5460508 A JPS5460508 A JP S5460508A JP 12685777 A JP12685777 A JP 12685777A JP 12685777 A JP12685777 A JP 12685777A JP S5460508 A JPS5460508 A JP S5460508A
Authority
JP
Japan
Prior art keywords
program
initial program
exchange
indication
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12685777A
Other languages
Japanese (ja)
Other versions
JPS5745517B2 (en
Inventor
Tsuguhiro Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12685777A priority Critical patent/JPS5460508A/en
Publication of JPS5460508A publication Critical patent/JPS5460508A/en
Publication of JPS5745517B2 publication Critical patent/JPS5745517B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54508—Configuration, initialisation
    • H04Q3/54516—Initialization, software or data downloading
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1305—Software aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13109—Initializing, personal profile
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13376—Information service, downloading of information, 0800/0900 services

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Information Transfer Between Computers (AREA)
  • Computer And Data Communications (AREA)

Abstract

PURPOSE:To omit the exclusive buffer memory and thus to ensure the effecitive use of the memory by editing the control part in the frame constitution and giving transmssion to other repeating exchange based on the indication given from the network control every time the program divided and controlled at the repeating exchange is received. CONSTITUTION:In case the program for loading the initial program is divided and controlled through network control center NCC15, the divided and controlled program edits the control part in the frame constitution and transmits it to repeating exchange 17 by the indication given from NCC15 and with every reception at repeating exchange 16. At exchange 17, no start indication is given for the initial program until the loading end indication control signal is recofnized. Thus, the buffer memory exclusive for the initial program loading can be omitted, ensuring the high-efficeincy use of the memory.
JP12685777A 1977-10-24 1977-10-24 Initial program loading system Granted JPS5460508A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12685777A JPS5460508A (en) 1977-10-24 1977-10-24 Initial program loading system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12685777A JPS5460508A (en) 1977-10-24 1977-10-24 Initial program loading system

Publications (2)

Publication Number Publication Date
JPS5460508A true JPS5460508A (en) 1979-05-16
JPS5745517B2 JPS5745517B2 (en) 1982-09-28

Family

ID=14945555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12685777A Granted JPS5460508A (en) 1977-10-24 1977-10-24 Initial program loading system

Country Status (1)

Country Link
JP (1) JPS5460508A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224594A (en) * 1985-03-28 1986-10-06 Nec Corp IPL activation device for satellite-mounted exchange

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6289449U (en) * 1985-11-25 1987-06-08

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224594A (en) * 1985-03-28 1986-10-06 Nec Corp IPL activation device for satellite-mounted exchange

Also Published As

Publication number Publication date
JPS5745517B2 (en) 1982-09-28

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