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JPS5448451A - Data fetching ststem - Google Patents

Data fetching ststem

Info

Publication number
JPS5448451A
JPS5448451A JP11459677A JP11459677A JPS5448451A JP S5448451 A JPS5448451 A JP S5448451A JP 11459677 A JP11459677 A JP 11459677A JP 11459677 A JP11459677 A JP 11459677A JP S5448451 A JPS5448451 A JP S5448451A
Authority
JP
Japan
Prior art keywords
signal
output
phi2
data
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11459677A
Other languages
Japanese (ja)
Inventor
Tatsuaki Ueno
Toshimasa Kihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11459677A priority Critical patent/JPS5448451A/en
Publication of JPS5448451A publication Critical patent/JPS5448451A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To prevent malfunction of ROM, by providing the selection circuit to deliver the data fectched based on the data processing unit and the synchronizing signal at least to a given memory element, and by performing the fetch of data to the selection circuit with the data fectch signal delayed from th synchronizing signal. CONSTITUTION:At the output point of the delay circuit A to which synchronzing signal phi2 is inputted, the signal V1 delayed from th signal phi2 is obtained, On the other hand, at the output of the AND gate G1 taking two inputs of the signal V1 and phi2, the signal V2 being 1 when the signal phi2 is 1 and V1 is 1. Further, at the output of the NOR gate circuit 2, the signal V3 being 1 when the signal phi2 is 0 and the signal V1 is 0 is obtained. Moreover, at the output of the NOR gata G3, the siganl phi2B being 0 when the output V2 of the circuit G1 is 0 and the output V3 of the circuit G2 is 0 is obtained. That is, the signal phi2B obtained to the signal phi2 has twice frequency. At this time, the objective can be achieved by utilizing the output V3 through the utilization of the signal V3 obtained with the inversion of 1, 0 with the inverter as the data fetch signal.
JP11459677A 1977-09-26 1977-09-26 Data fetching ststem Pending JPS5448451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11459677A JPS5448451A (en) 1977-09-26 1977-09-26 Data fetching ststem

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11459677A JPS5448451A (en) 1977-09-26 1977-09-26 Data fetching ststem

Publications (1)

Publication Number Publication Date
JPS5448451A true JPS5448451A (en) 1979-04-17

Family

ID=14641809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11459677A Pending JPS5448451A (en) 1977-09-26 1977-09-26 Data fetching ststem

Country Status (1)

Country Link
JP (1) JPS5448451A (en)

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