JPS5443653A - Automatic delay circuit - Google Patents
Automatic delay circuitInfo
- Publication number
- JPS5443653A JPS5443653A JP10985577A JP10985577A JPS5443653A JP S5443653 A JPS5443653 A JP S5443653A JP 10985577 A JP10985577 A JP 10985577A JP 10985577 A JP10985577 A JP 10985577A JP S5443653 A JPS5443653 A JP S5443653A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- time
- delay
- delay operation
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007493 shaping process Methods 0.000 abstract 2
- 230000005540 biological transmission Effects 0.000 abstract 1
- 230000003111 delayed effect Effects 0.000 abstract 1
Landscapes
- Networks Using Active Elements (AREA)
Abstract
PURPOSE: To give a required delay time to an input signal only by performing the delay operation according to requirement, by setting automatically the set value corresponding to the delay time in the circuit where the input signal is delayed and compensated and its phase is made coincide with the phase of the reference signal and the input signal is outputted.
CONSTITUTION: The first waveform shaping circuit 40 to shape input analogue signal 10 into a sqare wave and the second waveform shaping circuit 44 to shape reference signal 42 such as a transmission signal into a square wave are provided, and further, OR circuit 46 which compares output square waves of circuits 40 and 44 with each other at the delay operation time and outputs the exclusive OR of them and switching circuit 48 which switches the circuit at the delay operation time and at the delay operation complition time are provided. Then, pulse generator 50 to generate a pulse every fixed period, set counter 52 to count pulses from generator 50 only in the time corresponding to the phase difference detected by circuit 46 at the delay operation time, holding circuit 54 to hold the output of counter 52 and delay counter 14 to input the output of circuits 54 and 48 are provided.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10985577A JPS5443653A (en) | 1977-09-14 | 1977-09-14 | Automatic delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10985577A JPS5443653A (en) | 1977-09-14 | 1977-09-14 | Automatic delay circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5443653A true JPS5443653A (en) | 1979-04-06 |
| JPS5519527B2 JPS5519527B2 (en) | 1980-05-27 |
Family
ID=14520889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10985577A Granted JPS5443653A (en) | 1977-09-14 | 1977-09-14 | Automatic delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5443653A (en) |
-
1977
- 1977-09-14 JP JP10985577A patent/JPS5443653A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5519527B2 (en) | 1980-05-27 |
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