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JPS54161811A - Data transmission device - Google Patents

Data transmission device

Info

Publication number
JPS54161811A
JPS54161811A JP7129078A JP7129078A JPS54161811A JP S54161811 A JPS54161811 A JP S54161811A JP 7129078 A JP7129078 A JP 7129078A JP 7129078 A JP7129078 A JP 7129078A JP S54161811 A JPS54161811 A JP S54161811A
Authority
JP
Japan
Prior art keywords
circuit
bit number
data transmission
transmission
setting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7129078A
Other languages
Japanese (ja)
Inventor
Masaharu Hirooka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7129078A priority Critical patent/JPS54161811A/en
Publication of JPS54161811A publication Critical patent/JPS54161811A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To realize a highly flexible data transmission by setting the bit number allowing the error of the code pattern in correspondence to the optimum state of the transmission circuit. CONSTITUTION:The data of the time-series is supplied to input register 2 from input terminal 1 to be memorized temporarily, and then delivered to turn into the parallel data to be then supplied to simultaneous detection circuit in the form of the frame characters. Allowance bit number information setting circuit 5 is connected to circuit 3, and circuit 3 delivers the synchronous output signals based on the setting information delivered from circuit 5. Thus, the bit number allowing the error of the frame synchronous pattern is set in accordance with the optimum state of the transmission circuit. In such way, a highly flexible data transmission can be secured.
JP7129078A 1978-06-12 1978-06-12 Data transmission device Pending JPS54161811A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7129078A JPS54161811A (en) 1978-06-12 1978-06-12 Data transmission device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7129078A JPS54161811A (en) 1978-06-12 1978-06-12 Data transmission device

Publications (1)

Publication Number Publication Date
JPS54161811A true JPS54161811A (en) 1979-12-21

Family

ID=13456403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7129078A Pending JPS54161811A (en) 1978-06-12 1978-06-12 Data transmission device

Country Status (1)

Country Link
JP (1) JPS54161811A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693452A (en) * 1979-12-27 1981-07-29 Nec Corp Digital synchronization detecting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693452A (en) * 1979-12-27 1981-07-29 Nec Corp Digital synchronization detecting circuit

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