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JPS54161271A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54161271A
JPS54161271A JP7008078A JP7008078A JPS54161271A JP S54161271 A JPS54161271 A JP S54161271A JP 7008078 A JP7008078 A JP 7008078A JP 7008078 A JP7008078 A JP 7008078A JP S54161271 A JPS54161271 A JP S54161271A
Authority
JP
Japan
Prior art keywords
constitution
sealed
sealing
tube
thermal shrinkage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7008078A
Other languages
Japanese (ja)
Inventor
Koji Kawanami
Tetsuo Ichikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7008078A priority Critical patent/JPS54161271A/en
Publication of JPS54161271A publication Critical patent/JPS54161271A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: To improve the yield and reliability by resin-sealing after sealing one part of a lead wire and a semiconductor pellet by using a plastic-based thermal shrinkage tube.
CONSTITUTION: Lead wire 2' with projection part 4 and pellet 1 are sealed at a low temperature by polyolefin-based thermal shrinkage tube 5 with its internal surface coated with an adhesive fused by heating. Next, tube 5 and lead projection part 4 are completely resin-sealed 6. In this constitution, a device can be obtained which withstands shock tests and mechanical strain and is excellent in moistureproofness.
COPYRIGHT: (C)1979,JPO&Japio
JP7008078A 1978-06-09 1978-06-09 Semiconductor device Pending JPS54161271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7008078A JPS54161271A (en) 1978-06-09 1978-06-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7008078A JPS54161271A (en) 1978-06-09 1978-06-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54161271A true JPS54161271A (en) 1979-12-20

Family

ID=13421197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7008078A Pending JPS54161271A (en) 1978-06-09 1978-06-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54161271A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6320442U (en) * 1986-07-25 1988-02-10
JPS6320443U (en) * 1986-07-25 1988-02-10
US6214650B1 (en) 2000-02-01 2001-04-10 Lockheed Martin Corporation Method and apparatus for sealing a ball grid array package and circuit card interconnection

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6320442U (en) * 1986-07-25 1988-02-10
JPS6320443U (en) * 1986-07-25 1988-02-10
US6214650B1 (en) 2000-02-01 2001-04-10 Lockheed Martin Corporation Method and apparatus for sealing a ball grid array package and circuit card interconnection
US6459164B2 (en) 2000-02-01 2002-10-01 Lockheed Martin Corporation Apparatus for sealing a ball grid array package and circuit card interconnection

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