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JPS54159818A - Delay circuit - Google Patents

Delay circuit

Info

Publication number
JPS54159818A
JPS54159818A JP6833278A JP6833278A JPS54159818A JP S54159818 A JPS54159818 A JP S54159818A JP 6833278 A JP6833278 A JP 6833278A JP 6833278 A JP6833278 A JP 6833278A JP S54159818 A JPS54159818 A JP S54159818A
Authority
JP
Japan
Prior art keywords
composite video
horizontal synchronizing
video signals
signals
clock pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6833278A
Other languages
Japanese (ja)
Other versions
JPS6019871B2 (en
Inventor
Yoshihiko Ota
Yoshiteru Kosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP53068332A priority Critical patent/JPS6019871B2/en
Publication of JPS54159818A publication Critical patent/JPS54159818A/en
Publication of JPS6019871B2 publication Critical patent/JPS6019871B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE: To prevent the slippage of a picture by a variable delay element which has the delay quantity controlled by pulses synchronizing with horizontal synchronizing signals in delayed input composite video signals.
CONSTITUTION: Composite video signals coming from input terminal 1 are supplied to horizontal synchronizing signal separator circuit 6 and PLL 7 to obtain clock pulses which are synchronized with horizontal synchronizing signals. These clock pulses are applied to N-bit CCD 5 to take out composite video signals delayed by time γ, and clock frequency components are eliminated by LPF 9. Since clock pulses are synchronized with the phase of horizontal synchronizing signals, delay time γ is followed to prevent the picture from being double even if they have time base fluctuation components such as reproduced composite video signals.
COPYRIGHT: (C)1979,JPO&Japio
JP53068332A 1978-06-08 1978-06-08 dropout compensator Expired JPS6019871B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53068332A JPS6019871B2 (en) 1978-06-08 1978-06-08 dropout compensator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53068332A JPS6019871B2 (en) 1978-06-08 1978-06-08 dropout compensator

Publications (2)

Publication Number Publication Date
JPS54159818A true JPS54159818A (en) 1979-12-18
JPS6019871B2 JPS6019871B2 (en) 1985-05-18

Family

ID=13370767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53068332A Expired JPS6019871B2 (en) 1978-06-08 1978-06-08 dropout compensator

Country Status (1)

Country Link
JP (1) JPS6019871B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6369930U (en) * 1986-10-28 1988-05-11

Also Published As

Publication number Publication date
JPS6019871B2 (en) 1985-05-18

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