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JPS54157028A - Framing control unit of video signal recording device - Google Patents

Framing control unit of video signal recording device

Info

Publication number
JPS54157028A
JPS54157028A JP6537278A JP6537278A JPS54157028A JP S54157028 A JPS54157028 A JP S54157028A JP 6537278 A JP6537278 A JP 6537278A JP 6537278 A JP6537278 A JP 6537278A JP S54157028 A JPS54157028 A JP S54157028A
Authority
JP
Japan
Prior art keywords
signals
circuit
synchronizing
framing
synchronizing signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6537278A
Other languages
Japanese (ja)
Other versions
JPS6244469B2 (en
Inventor
Kenji Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP6537278A priority Critical patent/JPS54157028A/en
Publication of JPS54157028A publication Critical patent/JPS54157028A/en
Publication of JPS6244469B2 publication Critical patent/JPS6244469B2/ja
Granted legal-status Critical Current

Links

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  • Management Or Editing Of Information On Record Carriers (AREA)

Abstract

PURPOSE: To eliminate the disturbance of reproduced pictures by recording video signals, where same odd signals of odd or even field signals are continuous partially, on a magnetic tape, etc., where control signals are recorded at every frame period, synchronously with control signals.
CONSTITUTION: Synchronizing separator circuit 6 where input video signals from input terminal 5 are supplied to separate composite synchronizing signals and vertical synchronizing separator circuit 7 where composite synchronizing signals separated by circuit 6 are supplied to separate vertical synchronizing signals are provided, and further, framing synchronizing separator circuit 8 where composite synchronizing signals separated by circuit 6 are supplied to separate framing synchronizing signals is provided. Then, AND gate 9 which is connected to delay circuit 11 extracting framing synchronizing signals for a prescribed time from the recording start of video signals and FF circuit 12 which is triggerred by vertical synchronizing signals separated by circuit 7 and has the operation state regulated by framing synchronizing signals are provided, and framing control signals are outputted to output terminal 14 of FF circuit 12.
COPYRIGHT: (C)1979,JPO&Japio
JP6537278A 1978-05-31 1978-05-31 Framing control unit of video signal recording device Granted JPS54157028A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6537278A JPS54157028A (en) 1978-05-31 1978-05-31 Framing control unit of video signal recording device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6537278A JPS54157028A (en) 1978-05-31 1978-05-31 Framing control unit of video signal recording device

Publications (2)

Publication Number Publication Date
JPS54157028A true JPS54157028A (en) 1979-12-11
JPS6244469B2 JPS6244469B2 (en) 1987-09-21

Family

ID=13285059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6537278A Granted JPS54157028A (en) 1978-05-31 1978-05-31 Framing control unit of video signal recording device

Country Status (1)

Country Link
JP (1) JPS54157028A (en)

Also Published As

Publication number Publication date
JPS6244469B2 (en) 1987-09-21

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