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JPS54153559A - Signal conversion circuit - Google Patents

Signal conversion circuit

Info

Publication number
JPS54153559A
JPS54153559A JP6267278A JP6267278A JPS54153559A JP S54153559 A JPS54153559 A JP S54153559A JP 6267278 A JP6267278 A JP 6267278A JP 6267278 A JP6267278 A JP 6267278A JP S54153559 A JPS54153559 A JP S54153559A
Authority
JP
Japan
Prior art keywords
pulse
fetq
capacitor
potential
conversion circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6267278A
Other languages
Japanese (ja)
Inventor
Tojiro Takegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6267278A priority Critical patent/JPS54153559A/en
Publication of JPS54153559A publication Critical patent/JPS54153559A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To enable to obtan wide range of the dispersion in the integrated production process and to obtain low cost and highly accurate products, without being affected with the dispersion in the circuit elements constituting the A/O conversion circuit for the signal conversion circuit.
CONSTITUTION: When the pulse ϕs is at low level, IGFETQ1 is ON, and the input voltage V1 is written in the capacitor Cs. In this case, IGFETQ5 is ON and the storage charge in the capacitor C is discharged. When the pulse ϕs is at ground potential, FETQ1 is OFF and the charge Cs.V1 is stored in the capacitor Cs. Simultaneously, the potential at the node 2 is V1+Vo-Vp2. When the pulse ϕ1 in different phase is at low level, FETQ4 is ON and the node 4 of the capacitor C is charged up at the potential of VD-Vp1. That of another FETQ2 is at Vo-Vp1. Next, when the pulse ϕ1 is at ground potential and the pulse ϕ2 is at low level, FETQ5 is ON to discharge the charge. As a result, Vp2 can be selected so that the ground potential is made to the reference potential, independently of the dispersion in the manufacturing process.
COPYRIGHT: (C)1979,JPO&Japio
JP6267278A 1978-05-24 1978-05-24 Signal conversion circuit Pending JPS54153559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6267278A JPS54153559A (en) 1978-05-24 1978-05-24 Signal conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6267278A JPS54153559A (en) 1978-05-24 1978-05-24 Signal conversion circuit

Publications (1)

Publication Number Publication Date
JPS54153559A true JPS54153559A (en) 1979-12-03

Family

ID=13207006

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6267278A Pending JPS54153559A (en) 1978-05-24 1978-05-24 Signal conversion circuit

Country Status (1)

Country Link
JP (1) JPS54153559A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001481A (en) * 1990-01-30 1991-03-19 David Sarnoff Research Center, Inc. MOS transistor threshold compensation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001481A (en) * 1990-01-30 1991-03-19 David Sarnoff Research Center, Inc. MOS transistor threshold compensation circuit

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