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JPS54139514A - Time axis conversion circuit of signals - Google Patents

Time axis conversion circuit of signals

Info

Publication number
JPS54139514A
JPS54139514A JP4887378A JP4887378A JPS54139514A JP S54139514 A JPS54139514 A JP S54139514A JP 4887378 A JP4887378 A JP 4887378A JP 4887378 A JP4887378 A JP 4887378A JP S54139514 A JPS54139514 A JP S54139514A
Authority
JP
Japan
Prior art keywords
time axis
thru
vco
constitution
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4887378A
Other languages
Japanese (ja)
Inventor
Masaru Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP4887378A priority Critical patent/JPS54139514A/en
Publication of JPS54139514A publication Critical patent/JPS54139514A/en
Pending legal-status Critical Current

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  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)

Abstract

PURPOSE: To obtain the audio signal of compressed time axis with a simple constitution by subsequently changing the clocks of two analog shift registers such as BBD, etc. according to time axis change rates.
CONSTITUTION: BBDs 25, 26 and analogs 27, 28 are subjected respectively to clock control and switch control by the constitution of a write clock circuit 30 of a frequency fw, an N frequency dividing circuit 31 of the output of the circuit 30, a VCO 32 whose oscillation frequency fr changes according to control voltage, AND gates 33 thru 36, OR gates 37, 38. The VCO 32 oscillates according to the voltages controlled by way of the analog switches 42 thru 43 which are respectively continued by the control voltage generating circuits 30 thru 41 generating specified voltages according to the time axis change rates m indicated. The switches 42 thru 43 are subsequently opened and closed by a ring counter 45 which generates outputs subsequently at each N frequency division of the VCO 32.
COPYRIGHT: (C)1979,JPO&Japio
JP4887378A 1978-04-20 1978-04-20 Time axis conversion circuit of signals Pending JPS54139514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4887378A JPS54139514A (en) 1978-04-20 1978-04-20 Time axis conversion circuit of signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4887378A JPS54139514A (en) 1978-04-20 1978-04-20 Time axis conversion circuit of signals

Publications (1)

Publication Number Publication Date
JPS54139514A true JPS54139514A (en) 1979-10-30

Family

ID=12815399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4887378A Pending JPS54139514A (en) 1978-04-20 1978-04-20 Time axis conversion circuit of signals

Country Status (1)

Country Link
JP (1) JPS54139514A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6164666U (en) * 1984-09-29 1986-05-02

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6164666U (en) * 1984-09-29 1986-05-02
JPH0529520Y2 (en) * 1984-09-29 1993-07-28

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