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JPS54129946A - Data processor - Google Patents

Data processor

Info

Publication number
JPS54129946A
JPS54129946A JP3761978A JP3761978A JPS54129946A JP S54129946 A JPS54129946 A JP S54129946A JP 3761978 A JP3761978 A JP 3761978A JP 3761978 A JP3761978 A JP 3761978A JP S54129946 A JPS54129946 A JP S54129946A
Authority
JP
Japan
Prior art keywords
ilo
program
tracing
head address
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3761978A
Other languages
Japanese (ja)
Other versions
JPS5849901B2 (en
Inventor
Yuichi Kimihira
Akio Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP53037619A priority Critical patent/JPS5849901B2/en
Publication of JPS54129946A publication Critical patent/JPS54129946A/en
Publication of JPS5849901B2 publication Critical patent/JPS5849901B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To make it possible to read and trace an ILO program stored in a memory by providing a main memory, a channel controller, a pointer assigning the head address of the memory, and a tracing-function indicating method.
CONSTITUTION: By an input device, initial-loader ILO program 1 is stored in main memory MM3 via controller 2. At this time, the mode is set by operation-mode selection instruction 4 before the actuation, and it is set by ILO-number setting switch 5 which ILO should be made to run first. Next, after the head address of ILO to be executed is set to sequence counter SCC6, SCC6 is caused to count up, the ILO program is read out to unit 2, and the following control is moved to the ILO program. In addition, this processor is equipped with pointer 75 assigning the head address of the fixed region of MM, tracing-assignment switch 77 and channel controller 72; when a channel instruction is actuated, the tracing of a device number, etc., becomes possible and the abnormality of the program can be found.
COPYRIGHT: (C)1979,JPO&Japio
JP53037619A 1978-03-31 1978-03-31 data processing equipment Expired JPS5849901B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53037619A JPS5849901B2 (en) 1978-03-31 1978-03-31 data processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53037619A JPS5849901B2 (en) 1978-03-31 1978-03-31 data processing equipment

Publications (2)

Publication Number Publication Date
JPS54129946A true JPS54129946A (en) 1979-10-08
JPS5849901B2 JPS5849901B2 (en) 1983-11-07

Family

ID=12502631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53037619A Expired JPS5849901B2 (en) 1978-03-31 1978-03-31 data processing equipment

Country Status (1)

Country Link
JP (1) JPS5849901B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182766A (en) * 1982-04-20 1983-10-25 Nec Corp Program tracing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182766A (en) * 1982-04-20 1983-10-25 Nec Corp Program tracing device

Also Published As

Publication number Publication date
JPS5849901B2 (en) 1983-11-07

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