JPS54116166A - Data conversion circuit - Google Patents
Data conversion circuitInfo
- Publication number
- JPS54116166A JPS54116166A JP2300278A JP2300278A JPS54116166A JP S54116166 A JPS54116166 A JP S54116166A JP 2300278 A JP2300278 A JP 2300278A JP 2300278 A JP2300278 A JP 2300278A JP S54116166 A JPS54116166 A JP S54116166A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- fed
- power supply
- type mosfet
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 title abstract 2
- 230000000295 complement effect Effects 0.000 abstract 1
- 230000005236 sound signal Effects 0.000 abstract 1
Landscapes
- Dc Digital Transmission (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
PURPOSE: To obtain the conversion circuit of low cost with a simple constitution, by providing the complementary MOS inversion circuit of cascade connection for an odd number of stages, and with the circuit constitution that each odd number stage performs switching operation between the first power supply voltages and each even number stage performs it in opposite phase between the second power supply voltages.
CONSTITUTION: In the reproduction of data recorded on the magnetic tape, the audio signal recorded is fed to the MOS inversion circuit I1 via the inverters 14, 16. In the circuit I1, P type MOSFET 17, 18 and N type MOSFET 19, 20 are connected in series between the first power supply 5V and the second power supply ground, the gate of FET 17 is grounded and clock pulse ϕ is fed to the gate of FET 20. The output signal Sg of the circuit I1 is fed to the inversion circuit I2, which consists of the series connection of P type MOSFET 21, 22 and N type MOSFET 23, 24, and clock ϕ is fed to the gate of FET 21. The output signal Sh of the circuit I2 is fed to the inversion circuit I3 of the same constitution as the circuit I1, and the output signal Si is outputted from the terminal DOUT. Accordingly, even if the phase between the input signal and the clock ϕ is different, the data can be converted as shown in Figure.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53023002A JPS5811136B2 (en) | 1978-03-01 | 1978-03-01 | data conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53023002A JPS5811136B2 (en) | 1978-03-01 | 1978-03-01 | data conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54116166A true JPS54116166A (en) | 1979-09-10 |
| JPS5811136B2 JPS5811136B2 (en) | 1983-03-01 |
Family
ID=12098286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53023002A Expired JPS5811136B2 (en) | 1978-03-01 | 1978-03-01 | data conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5811136B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59157352U (en) * | 1983-04-08 | 1984-10-22 | 三菱電機株式会社 | Optical transmitter/receiver for digital signal transmission |
-
1978
- 1978-03-01 JP JP53023002A patent/JPS5811136B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59157352U (en) * | 1983-04-08 | 1984-10-22 | 三菱電機株式会社 | Optical transmitter/receiver for digital signal transmission |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5811136B2 (en) | 1983-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS52119160A (en) | Semiconductor circuit with insulating gate type field dffect transisto r | |
| JPS6437797A (en) | Eprom device | |
| JPS6471217A (en) | Output buffer circuit | |
| JPS57111810A (en) | Digital signal processor | |
| KR930009432B1 (en) | Current element for digital / analog converter | |
| KR830002451A (en) | Sense amplifier | |
| EP0895356A3 (en) | Signal change detection circuit | |
| JPS5696532A (en) | Frequency divider | |
| JPS56124195A (en) | Dynamic shift register circuit | |
| JPS6462019A (en) | Mos transistor circuit | |
| JPS54116166A (en) | Data conversion circuit | |
| ES542409A0 (en) | "A SEMICONDUCTOR DEVICE COUPLED IN LOAD" | |
| FR2379198A1 (en) | Two phase logic clock source - is based on cross coupled NAND=gates driven from common source | |
| SU1319249A1 (en) | Digital-analog delay line based on charge transfer devices | |
| JPS523353A (en) | Integrated logic circuit | |
| SU513376A1 (en) | Device for generating signaling signals of the group of analog magnetographs | |
| SU539378A1 (en) | Semi-adder | |
| JPH0431630Y2 (en) | ||
| JPS5775027A (en) | Level shift circuit | |
| JPS5373047A (en) | Generation circuit for timing signal | |
| JPS5623023A (en) | Input buffer circuit | |
| JPS5863892U (en) | inverter circuit | |
| JPS54102985A (en) | Semiconductor integrated circuit | |
| JPS5342681A (en) | High frequency compound transistor | |
| JPH0376560B2 (en) |