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JPS54109729A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS54109729A
JPS54109729A JP1716078A JP1716078A JPS54109729A JP S54109729 A JPS54109729 A JP S54109729A JP 1716078 A JP1716078 A JP 1716078A JP 1716078 A JP1716078 A JP 1716078A JP S54109729 A JPS54109729 A JP S54109729A
Authority
JP
Japan
Prior art keywords
source
drain
cross connection
resistance
fetq3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1716078A
Other languages
Japanese (ja)
Other versions
JPS6240792B2 (en
Inventor
Isamu Miyagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1716078A priority Critical patent/JPS54109729A/en
Publication of JPS54109729A publication Critical patent/JPS54109729A/en
Publication of JPS6240792B2 publication Critical patent/JPS6240792B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To realize a large-capacity monolithic memory by giving a cross connection to the gate and source of a pair of FET's and then connecting the drain, etc. of other pair of FET's which contain the resistance connected in parallel between the source and drain. CONSTITUTION:A cross connection is given between the gates of FETQ3 and Q4 of one side and the drains or source of FETQ1 and Q2 of the other side, and the sources or drains are connected and earthed in common. In this case, the gate and source of FETQ3 and Q4 gives the cross connection to the drain, and the drain or the source of FETQ1 and Q2 with resistance R1 and R2 connected in parallel between the source and drain is connected at the junction of the cross connection. As a result, the value of resistance R1 and R2 can be increased to hold the circuit state, and then the resistance value is decreased to carry out the writing or reading with the circuit. In this way, both the power line and the information line can be used in combination, thus realizing a large-capacity monolithic device.
JP1716078A 1978-02-16 1978-02-16 Memory circuit Granted JPS54109729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1716078A JPS54109729A (en) 1978-02-16 1978-02-16 Memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1716078A JPS54109729A (en) 1978-02-16 1978-02-16 Memory circuit

Publications (2)

Publication Number Publication Date
JPS54109729A true JPS54109729A (en) 1979-08-28
JPS6240792B2 JPS6240792B2 (en) 1987-08-31

Family

ID=11936209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1716078A Granted JPS54109729A (en) 1978-02-16 1978-02-16 Memory circuit

Country Status (1)

Country Link
JP (1) JPS54109729A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56114192A (en) * 1980-01-30 1981-09-08 Mostek Corp Ic memory
JP4837051B2 (en) * 2006-02-22 2011-12-14 グラフィック パッケージング インターナショナル インコーポレイテッド Flat blank carton

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS526037A (en) * 1975-06-30 1977-01-18 Ibm Semiconductor memory array
JPS5291622A (en) * 1976-01-28 1977-08-02 Nec Corp Static memory cell

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS526037A (en) * 1975-06-30 1977-01-18 Ibm Semiconductor memory array
JPS5291622A (en) * 1976-01-28 1977-08-02 Nec Corp Static memory cell

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56114192A (en) * 1980-01-30 1981-09-08 Mostek Corp Ic memory
JP4837051B2 (en) * 2006-02-22 2011-12-14 グラフィック パッケージング インターナショナル インコーポレイテッド Flat blank carton
US8127518B2 (en) 2006-02-22 2012-03-06 Graphic Packaging International, Inc. Flat blank carton

Also Published As

Publication number Publication date
JPS6240792B2 (en) 1987-08-31

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