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JPS54105937A - Monitor system for electronic computer system - Google Patents

Monitor system for electronic computer system

Info

Publication number
JPS54105937A
JPS54105937A JP1240878A JP1240878A JPS54105937A JP S54105937 A JPS54105937 A JP S54105937A JP 1240878 A JP1240878 A JP 1240878A JP 1240878 A JP1240878 A JP 1240878A JP S54105937 A JPS54105937 A JP S54105937A
Authority
JP
Japan
Prior art keywords
cpu
monitor
interruption
state
under
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1240878A
Other languages
Japanese (ja)
Other versions
JPS5819097B2 (en
Inventor
Shinichi Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53012408A priority Critical patent/JPS5819097B2/en
Publication of JPS54105937A publication Critical patent/JPS54105937A/en
Publication of JPS5819097B2 publication Critical patent/JPS5819097B2/en
Expired legal-status Critical Current

Links

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To constitute the supervisory unit in a simple and economical way by informing the state of other processors of the system simultaneously with the monitor interruption of a processor.
CONSTITUTION: Supervisory device SUP receives monitor start command (a) and then applies the monitor interruption to CPU (A)W(C) via monitor signal line SIG with a fixed time interval to send monitor interruption data (c). (In this case, AWC are set to "00" when CPU (A)W(C) are under stop state, set to "01" under monitoring state and set to "10" under the erroneous state respectively.) Thus, the CPU which received application of the interruption can know the state of other CPU's through data (c), accordingly carrying out the processes such as the system constitution, alteration and others without receiving the fault occurrence information especially. The CPU starts the time monitoring for the answer from CPU after applying the monitor interruption. And in case no answer is received in a fixed time, the fact that the CPU has some fault is decided to set the corresponding bits AWC to "10".
COPYRIGHT: (C)1979,JPO&Japio
JP53012408A 1978-02-08 1978-02-08 Computer system monitoring method Expired JPS5819097B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53012408A JPS5819097B2 (en) 1978-02-08 1978-02-08 Computer system monitoring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53012408A JPS5819097B2 (en) 1978-02-08 1978-02-08 Computer system monitoring method

Publications (2)

Publication Number Publication Date
JPS54105937A true JPS54105937A (en) 1979-08-20
JPS5819097B2 JPS5819097B2 (en) 1983-04-16

Family

ID=11804427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53012408A Expired JPS5819097B2 (en) 1978-02-08 1978-02-08 Computer system monitoring method

Country Status (1)

Country Link
JP (1) JPS5819097B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61194540A (en) * 1985-02-22 1986-08-28 Nec Corp Stall detection system
JPH03288938A (en) * 1990-04-05 1991-12-19 Fujitsu Ltd Composite computer with survival confirmation function

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61194540A (en) * 1985-02-22 1986-08-28 Nec Corp Stall detection system
JPH03288938A (en) * 1990-04-05 1991-12-19 Fujitsu Ltd Composite computer with survival confirmation function

Also Published As

Publication number Publication date
JPS5819097B2 (en) 1983-04-16

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