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JPS54103666A - Information display system - Google Patents

Information display system

Info

Publication number
JPS54103666A
JPS54103666A JP1071478A JP1071478A JPS54103666A JP S54103666 A JPS54103666 A JP S54103666A JP 1071478 A JP1071478 A JP 1071478A JP 1071478 A JP1071478 A JP 1071478A JP S54103666 A JPS54103666 A JP S54103666A
Authority
JP
Japan
Prior art keywords
gate
displayed
display unit
counter
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1071478A
Other languages
Japanese (ja)
Inventor
Chiaki Katsumi
Naoki Hamada
Akihisa Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1071478A priority Critical patent/JPS54103666A/en
Publication of JPS54103666A publication Critical patent/JPS54103666A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/18—Circuits for visual indication of the result

Landscapes

  • Measuring Frequencies, Analyzing Spectra (AREA)

Abstract

PURPOSE:To simplify the circuit constitution in case the various information quantity are displayed in a digital way through the common display unit by omitting the driver circuit for the display unit and also converting the information into the frequency via the frequency counter to carry out the digital display. CONSTITUTION:In case the measured frequency is displayed as the normal frequency counter, switch 5 is connected to side 4. And the counting is carried out via the frequency counter incorporating the driver circuit, and the display is given via display unit 7. Then in case the contents of the clock is displayed, switch 5 is connected to the clock side. And gate signal 8 sent from frequency counter 6 is used along with reference pulse 9, and pulse 9 passes AND gate 10 while siginal 8 is at H level. Then the number of the pulses passed through gate 10 is counted by down- counter 11 which is preset previously with the contents of clock 14, and the AND gate is closed when the count number becomes O. Meanwhile pulse number 13 which passed through the AND gate is counted via counter 6 and then displayed through display unit 7. Thus, the driver circuit can be omitted.
JP1071478A 1978-02-01 1978-02-01 Information display system Pending JPS54103666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1071478A JPS54103666A (en) 1978-02-01 1978-02-01 Information display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1071478A JPS54103666A (en) 1978-02-01 1978-02-01 Information display system

Publications (1)

Publication Number Publication Date
JPS54103666A true JPS54103666A (en) 1979-08-15

Family

ID=11757960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1071478A Pending JPS54103666A (en) 1978-02-01 1978-02-01 Information display system

Country Status (1)

Country Link
JP (1) JPS54103666A (en)

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