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JPS54102817A - Multi-frame synchronization system - Google Patents

Multi-frame synchronization system

Info

Publication number
JPS54102817A
JPS54102817A JP910678A JP910678A JPS54102817A JP S54102817 A JPS54102817 A JP S54102817A JP 910678 A JP910678 A JP 910678A JP 910678 A JP910678 A JP 910678A JP S54102817 A JPS54102817 A JP S54102817A
Authority
JP
Japan
Prior art keywords
frame
bit
synchronization
constitution
step out
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP910678A
Other languages
Japanese (ja)
Other versions
JPS588782B2 (en
Inventor
Hitoshi Imagawa
Tetsuaki Egawa
Shiro Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP53009106A priority Critical patent/JPS588782B2/en
Publication of JPS54102817A publication Critical patent/JPS54102817A/en
Publication of JPS588782B2 publication Critical patent/JPS588782B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To use for a time-division switchboard, etc., a system of economical constitution which can shorten front and back protective times, by inserting a multi- frame-synchronous bit with a sequence relation with a sequence relation established into each frame. CONSTITUTION:In order to discriminate a frame number given to each frame within one multi-frame, a pattern (binary code) expressing the frame number using multi-frame synchronous bit 1 in each frame is inserted into each frame. When multi-frame synchronization can not be made, dissidence signal 17 is outputted from comparator circuit 9 to synchronization protective circuit 10, which generates its output 18 in case of a step out, so that selector 11 will be switched. At this time, since discrimination 9 whether a step out or not is done for each frame, front and back protective times are shortened remarkably and bit 1 expresses the frame number as it is, so that the hardware can be constituted economically.
JP53009106A 1978-01-30 1978-01-30 Multi-frame synchronizer Expired JPS588782B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53009106A JPS588782B2 (en) 1978-01-30 1978-01-30 Multi-frame synchronizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53009106A JPS588782B2 (en) 1978-01-30 1978-01-30 Multi-frame synchronizer

Publications (2)

Publication Number Publication Date
JPS54102817A true JPS54102817A (en) 1979-08-13
JPS588782B2 JPS588782B2 (en) 1983-02-17

Family

ID=11711369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53009106A Expired JPS588782B2 (en) 1978-01-30 1978-01-30 Multi-frame synchronizer

Country Status (1)

Country Link
JP (1) JPS588782B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6039937A (en) * 1983-08-15 1985-03-02 Fujitsu Ltd Synchronization method
EP0134817A1 (en) * 1982-12-30 1985-03-27 Sony Corporation Method of transferring digital signal

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4990415A (en) * 1972-12-28 1974-08-29

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4990415A (en) * 1972-12-28 1974-08-29

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0134817A1 (en) * 1982-12-30 1985-03-27 Sony Corporation Method of transferring digital signal
EP0134817B1 (en) * 1982-12-30 1991-02-27 Sony Corporation Method of transferring digital signal
JPS6039937A (en) * 1983-08-15 1985-03-02 Fujitsu Ltd Synchronization method
JPH0134490B2 (en) * 1983-08-15 1989-07-19 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS588782B2 (en) 1983-02-17

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