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JPS5397381A - Nonvoltile semiconductor memory - Google Patents

Nonvoltile semiconductor memory

Info

Publication number
JPS5397381A
JPS5397381A JP1163877A JP1163877A JPS5397381A JP S5397381 A JPS5397381 A JP S5397381A JP 1163877 A JP1163877 A JP 1163877A JP 1163877 A JP1163877 A JP 1163877A JP S5397381 A JPS5397381 A JP S5397381A
Authority
JP
Japan
Prior art keywords
nonvoltile
semiconductor memory
density
writing
securing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1163877A
Other languages
Japanese (ja)
Inventor
Hiroshi Nozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1163877A priority Critical patent/JPS5397381A/en
Publication of JPS5397381A publication Critical patent/JPS5397381A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels

Landscapes

  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To increase both the writing and the reading velocity, by pushing in the high-density ion injection layer through the lateral diffusion only form the drain side using the floating gate as the mask and securing a density slope in the channel direction.
JP1163877A 1977-02-07 1977-02-07 Nonvoltile semiconductor memory Pending JPS5397381A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1163877A JPS5397381A (en) 1977-02-07 1977-02-07 Nonvoltile semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1163877A JPS5397381A (en) 1977-02-07 1977-02-07 Nonvoltile semiconductor memory

Publications (1)

Publication Number Publication Date
JPS5397381A true JPS5397381A (en) 1978-08-25

Family

ID=11783474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1163877A Pending JPS5397381A (en) 1977-02-07 1977-02-07 Nonvoltile semiconductor memory

Country Status (1)

Country Link
JP (1) JPS5397381A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5664469A (en) * 1979-09-04 1981-06-01 Texas Instruments Inc Programmable nonnvolatile floating gate type semiconductor memory device and method of manufacturing same
JPS62276878A (en) * 1986-05-26 1987-12-01 Hitachi Ltd Semiconductor memory
JPH0354869A (en) * 1989-07-21 1991-03-08 Seiko Instr Inc Semiconductor non-volatile memory
US5424567A (en) * 1991-05-15 1995-06-13 North American Philips Corporation Protected programmable transistor with reduced parasitic capacitances and method of fabrication
US5472891A (en) * 1986-05-26 1995-12-05 Hitachi, Ltd. Method of manufacturing a semiconductor device
US5904518A (en) * 1988-11-09 1999-05-18 Hitachi, Ltd. Method of manufacturing a semiconductor IC device having single transistor type nonvolatile memory cells
US6236085B1 (en) 1996-11-11 2001-05-22 Denso Corporation Semiconductor memory device having high-concentration region around electric-field moderating layer in substrate

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5664469A (en) * 1979-09-04 1981-06-01 Texas Instruments Inc Programmable nonnvolatile floating gate type semiconductor memory device and method of manufacturing same
US5472891A (en) * 1986-05-26 1995-12-05 Hitachi, Ltd. Method of manufacturing a semiconductor device
JPS62276878A (en) * 1986-05-26 1987-12-01 Hitachi Ltd Semiconductor memory
US6451643B2 (en) 1988-11-09 2002-09-17 Hitachi, Ltd. Method of manufacturing a semiconductor device having non-volatile memory cell portion with single transistor type memory cells and peripheral portion with MISFETs
US5904518A (en) * 1988-11-09 1999-05-18 Hitachi, Ltd. Method of manufacturing a semiconductor IC device having single transistor type nonvolatile memory cells
US6255690B1 (en) 1988-11-09 2001-07-03 Hitachi, Ltd. Non-volatile semiconductor memory device
US6777282B2 (en) 1988-11-09 2004-08-17 Renesas Technology Corp. Method of manufacturing a semiconductor memory device having a memory cell portion including MISFETs with a floating gate and a peripheral circuit portion with MISFETs
US6960501B2 (en) 1988-11-09 2005-11-01 Renesas Technology Corp. Method of manufacturing a semiconductor memory device having a non-volatile memory cell portion with single misfet transistor type memory cells and a peripheral circuit portion with misfets
US7071050B2 (en) 1988-11-09 2006-07-04 Hitachi, Ltd. Semiconductor integrated circuit device having single-element type non-volatile memory elements
US7399667B2 (en) 1988-11-09 2008-07-15 Renesas Technology Corp. Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements
JPH0354869A (en) * 1989-07-21 1991-03-08 Seiko Instr Inc Semiconductor non-volatile memory
US5424567A (en) * 1991-05-15 1995-06-13 North American Philips Corporation Protected programmable transistor with reduced parasitic capacitances and method of fabrication
US5486480A (en) * 1991-05-15 1996-01-23 North American Philips Corporation Method of fabrication of protected programmable transistor with reduced parasitic capacitances
US6236085B1 (en) 1996-11-11 2001-05-22 Denso Corporation Semiconductor memory device having high-concentration region around electric-field moderating layer in substrate

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