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JPS5397367A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS5397367A
JPS5397367A JP1272077A JP1272077A JPS5397367A JP S5397367 A JPS5397367 A JP S5397367A JP 1272077 A JP1272077 A JP 1272077A JP 1272077 A JP1272077 A JP 1272077A JP S5397367 A JPS5397367 A JP S5397367A
Authority
JP
Japan
Prior art keywords
manufacture
semiconductor device
lead surface
assured
gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1272077A
Other languages
Japanese (ja)
Inventor
Takashi Masamoto
Hiroshi Isoya
Hikari Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1272077A priority Critical patent/JPS5397367A/en
Publication of JPS5397367A publication Critical patent/JPS5397367A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To form the two layers of gold and tin on the lead surface of the tape carrier and to ensure an assured junction between the electrode and the lead surface through a short-time heat pressure bonding.
COPYRIGHT: (C)1978,JPO&Japio
JP1272077A 1977-02-07 1977-02-07 Semiconductor device and its manufacture Pending JPS5397367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1272077A JPS5397367A (en) 1977-02-07 1977-02-07 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1272077A JPS5397367A (en) 1977-02-07 1977-02-07 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS5397367A true JPS5397367A (en) 1978-08-25

Family

ID=11813254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1272077A Pending JPS5397367A (en) 1977-02-07 1977-02-07 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS5397367A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02209742A (en) * 1988-09-16 1990-08-21 Natl Semiconductor Corp <Ns> Gold/tin entectic bonding for tape automaization bonding process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02209742A (en) * 1988-09-16 1990-08-21 Natl Semiconductor Corp <Ns> Gold/tin entectic bonding for tape automaization bonding process

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