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JPS5373069A - Structure of lead frame for semiconductor element - Google Patents

Structure of lead frame for semiconductor element

Info

Publication number
JPS5373069A
JPS5373069A JP14963076A JP14963076A JPS5373069A JP S5373069 A JPS5373069 A JP S5373069A JP 14963076 A JP14963076 A JP 14963076A JP 14963076 A JP14963076 A JP 14963076A JP S5373069 A JPS5373069 A JP S5373069A
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor element
lead
frame
fabricate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14963076A
Other languages
Japanese (ja)
Other versions
JPS5642140B2 (en
Inventor
Yoshiaki Sano
Kazuya Takahashi
Hiroshi Mugitani
Muneyasu Tomiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14963076A priority Critical patent/JPS5373069A/en
Publication of JPS5373069A publication Critical patent/JPS5373069A/en
Publication of JPS5642140B2 publication Critical patent/JPS5642140B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Electric Clocks (AREA)

Abstract

PURPOSE:To fabricate a frame combination-used for lead-needed and lead-unneeded connection by making the tip of the lead frame into a two forked shaped.
JP14963076A 1976-12-13 1976-12-13 Structure of lead frame for semiconductor element Granted JPS5373069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14963076A JPS5373069A (en) 1976-12-13 1976-12-13 Structure of lead frame for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14963076A JPS5373069A (en) 1976-12-13 1976-12-13 Structure of lead frame for semiconductor element

Publications (2)

Publication Number Publication Date
JPS5373069A true JPS5373069A (en) 1978-06-29
JPS5642140B2 JPS5642140B2 (en) 1981-10-02

Family

ID=15479416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14963076A Granted JPS5373069A (en) 1976-12-13 1976-12-13 Structure of lead frame for semiconductor element

Country Status (1)

Country Link
JP (1) JPS5373069A (en)

Also Published As

Publication number Publication date
JPS5642140B2 (en) 1981-10-02

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