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JPS5335447A - Multi processor system - Google Patents

Multi processor system

Info

Publication number
JPS5335447A
JPS5335447A JP10943076A JP10943076A JPS5335447A JP S5335447 A JPS5335447 A JP S5335447A JP 10943076 A JP10943076 A JP 10943076A JP 10943076 A JP10943076 A JP 10943076A JP S5335447 A JPS5335447 A JP S5335447A
Authority
JP
Japan
Prior art keywords
processor system
multi processor
preventign
catching
hardware
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10943076A
Other languages
Japanese (ja)
Inventor
Akito Harada
Akira Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP10943076A priority Critical patent/JPS5335447A/en
Publication of JPS5335447A publication Critical patent/JPS5335447A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To make possible for the test and set instruction processing, without adding any hardware to the common memory, by receiving the usage request from each processor, allowing this in order, and preventign the multi catching of the common bus.
COPYRIGHT: (C)1978,JPO&Japio
JP10943076A 1976-09-14 1976-09-14 Multi processor system Pending JPS5335447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10943076A JPS5335447A (en) 1976-09-14 1976-09-14 Multi processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10943076A JPS5335447A (en) 1976-09-14 1976-09-14 Multi processor system

Publications (1)

Publication Number Publication Date
JPS5335447A true JPS5335447A (en) 1978-04-01

Family

ID=14510035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10943076A Pending JPS5335447A (en) 1976-09-14 1976-09-14 Multi processor system

Country Status (1)

Country Link
JP (1) JPS5335447A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60112857U (en) * 1983-12-29 1985-07-31 新明和工業株式会社 Data transfer circuit between microprocessors
JPS62237563A (en) * 1986-04-02 1987-10-17 ジ−メンス・アクチエンゲゼルシヤフト Method and apparatus for controlling one common memory of a multiprocessor system consisting of a plurality of individual microprocessor systems
JPS63168758A (en) * 1987-01-07 1988-07-12 Fujitsu Ltd Multi-bus control method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4941043A (en) * 1972-08-26 1974-04-17
JPS5091234A (en) * 1973-12-12 1975-07-21

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4941043A (en) * 1972-08-26 1974-04-17
JPS5091234A (en) * 1973-12-12 1975-07-21

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60112857U (en) * 1983-12-29 1985-07-31 新明和工業株式会社 Data transfer circuit between microprocessors
JPS62237563A (en) * 1986-04-02 1987-10-17 ジ−メンス・アクチエンゲゼルシヤフト Method and apparatus for controlling one common memory of a multiprocessor system consisting of a plurality of individual microprocessor systems
JPS63168758A (en) * 1987-01-07 1988-07-12 Fujitsu Ltd Multi-bus control method

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