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JPS51147133A - Non-voratile insulation gate semiconductor memory - Google Patents

Non-voratile insulation gate semiconductor memory

Info

Publication number
JPS51147133A
JPS51147133A JP7158375A JP7158375A JPS51147133A JP S51147133 A JPS51147133 A JP S51147133A JP 7158375 A JP7158375 A JP 7158375A JP 7158375 A JP7158375 A JP 7158375A JP S51147133 A JPS51147133 A JP S51147133A
Authority
JP
Japan
Prior art keywords
voratile
semiconductor memory
gate semiconductor
insulation gate
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7158375A
Other languages
Japanese (ja)
Other versions
JPS5610716B2 (en
Inventor
Michitoku Kamatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7158375A priority Critical patent/JPS51147133A/en
Publication of JPS51147133A publication Critical patent/JPS51147133A/en
Publication of JPS5610716B2 publication Critical patent/JPS5610716B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:Prevention of mutual interference by commonly grounding the sources of transistor through write-in transistor with proper resistance.
JP7158375A 1975-06-12 1975-06-12 Non-voratile insulation gate semiconductor memory Granted JPS51147133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7158375A JPS51147133A (en) 1975-06-12 1975-06-12 Non-voratile insulation gate semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7158375A JPS51147133A (en) 1975-06-12 1975-06-12 Non-voratile insulation gate semiconductor memory

Publications (2)

Publication Number Publication Date
JPS51147133A true JPS51147133A (en) 1976-12-17
JPS5610716B2 JPS5610716B2 (en) 1981-03-10

Family

ID=13464849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7158375A Granted JPS51147133A (en) 1975-06-12 1975-06-12 Non-voratile insulation gate semiconductor memory

Country Status (1)

Country Link
JP (1) JPS51147133A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4915380A (en) * 1972-05-18 1974-02-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4915380A (en) * 1972-05-18 1974-02-09

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Also Published As

Publication number Publication date
JPS5610716B2 (en) 1981-03-10

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