JPH1187538A - Nonvolatile semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which enables high speed reading, without increasing the area of a cell and provided a method for easily manufacturing the memory device. SOLUTION: A selection gate and a control gate 8 of a nonvolatile semiconductor memory device 10 are electrically connected to each other, and a floating gate 9 of a memory device 10 is electrically isolated from them. A groove 2 is formed on the main surface of a semiconductor substrate 1 and a source has a 1st source part 4 and a 2nd source part 6, which are formed on the bottom surface 3 of the groove 2 and on a side surface 5 of the groove 2, respectively. The impurity concentration of the 1st source part 4 is higher than that of a 2nd source part 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an electrically erasable nonvolatile semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional flash memory as an electrically erasable nonvolatile semiconductor memory device will be described with reference to FIGS. 8 and 9. FIG. FIG. 8 is a cross-sectional view illustrating an example of a conventional split gate flash memory. FIG.
FIG. 1 is a cross-sectional view illustrating an example of a conventional stack type flash memory. An advantage of the split gate type flash memory shown in FIG. 8 is that the threshold on the low level side is determined by the select gate transistor. As a result, in the split type flash memory, compared with the threshold value variation of the stack type flash memory, the threshold value variation on the low level side can be suppressed considerably smaller, and the read voltage can be easily reduced.

Further, in the split gate type flash memory 51 shown in FIG. 9, since the threshold value of the memory cell portion can be reduced so as to be sufficiently depleted, the on-current can be increased even if the channel length becomes long. , High-speed reading can be realized.

Next, a method for manufacturing a conventional split gate flash memory will be described with reference to FIGS. First, after an element isolation region is formed in the semiconductor substrate 1 of the first conductivity type, as shown in FIG. 10, a first insulating film 11 (about 100
Å) and the first conductive layer 9 serving as a floating gate
(About 1500 °) and the first interpoly insulating film 12 (silicon oxide film + silicon nitride film + silicon oxide film,
200 °).

Next, as shown in FIG. 11, the first inter-poly insulating film 12 and the first conductive layer 9 are patterned. At this time, the first conductive layer 9 is removed from a region that will later become the source 4 and a region that will later become the channel (second channel) 14 of the select transistor. Next, the side surface of the first conductive layer 9 and the region serving as the second channel 14 of the select transistor are thermally oxidized to form a second poly-poly insulating film 16 made of a silicon oxide film of about 250 ° (see FIG. 12). To form

Next, as shown in FIG. 12, a second conductive layer 8 (polysilicon + tungsten silicide, 1500 + 1500 °) to be a control gate is formed.

Subsequently, as shown in FIG. 13, the first conductive layer 9, the first inter-poly insulating film 12, and the second conductive layer 8 are simultaneously formed from a region to be a drain 7 later. Etch. Reference numeral 13 denotes a first channel serving as a channel of the memory cell unit. Reference numeral 15 denotes a second insulating film formed on the second channel 14.

Next, as shown in FIG.
The second conductive layer 8 is etched from above the region to be.

Next, as shown in FIG. 15, arsenic (about 5E15 / cm ² ) is implanted using the control gate 8 as a mask to form a source 4 and a drain 7, thereby forming a flash memory cell.

[0010]

In the conventional split gate type flash memory, since it is necessary to cut off the current in each of the select transistor section and the memory cell section, the cell size is increased by the amount of the select transistor. There was a problem. Various measures have been taken to avoid this. For example, JP-A-6-3500
As disclosed in Japanese Unexamined Patent Publication No. 95 (referred to as Prior Art 1), a method of digging a groove and embedding a floating gate is one such method. According to the prior art 1, by burying a floating gate by digging a groove, the side wall of the groove can also be used as a channel, so that the area occupied by the channel region can be reduced without reducing the channel length.

However, in this method, it is difficult to form a gate oxide film or a floating gate accurately on the side surface of the groove, and the floating gate is embedded in the groove. For,
There is a problem that the area in contact with the control gate is reduced, and as a result, the capacitance ratio is reduced.

It is an object of the present invention to provide a nonvolatile semiconductor memory device which can perform high-speed reading without increasing the cell area in the nonvolatile semiconductor memory device.

Another technical object of the present invention is to provide a method for easily forming the above-mentioned nonvolatile semiconductor memory device.

[0014]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a source and a drain of a second conductivity type formed on a main surface of a semiconductor substrate of a first conductivity type; A first channel region and a second channel region formed therebetween, a tunnel gate insulating film formed on the first channel region, and a select gate insulating film formed on the second channel region And the first
A gate formed on the floating gate, an inter-poly insulating film formed on the floating gate, a control gate formed on the inter-poly insulating film, and a select gate formed on the select gate insulating film Wherein the select gate and the control gate are electrically connected and the floating gate is electrically insulated, and is formed in a groove which is recessed in the substrate from the main surface of the semiconductor substrate surface forming the drain. The source is formed.

Further, in the nonvolatile semiconductor memory device according to the present invention, in the nonvolatile semiconductor memory device, the source is formed on a first source portion formed on a bottom surface of the groove and on a side surface of the groove. And a second source section.

Further, in the nonvolatile semiconductor memory device according to the present invention, in the nonvolatile semiconductor memory device, an impurity concentration of the first source portion is higher than an impurity concentration of the second source portion.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of forming a first insulating film serving as a tunnel gate insulating film on a main surface of a semiconductor substrate of a first conductivity type; Forming a first conductive layer to be a floating gate on the first gate insulating film; forming a second insulating film on the first conductive layer; Etching the first conductive layer;
Forming a third insulating film on the channel region and the side surface of the first conductive layer; and forming the second insulating film and the third
Forming a second conductive layer serving as a control gate and a select gate on the insulating film, and forming the second conductive layer, the second insulating film, the third insulating film, and the first conductive layer.
Simultaneously etching the conductive film and the semiconductor substrate, implanting impurity ions in a direction perpendicular to the semiconductor substrate, and implanting impurity ions in an oblique direction to the semiconductor substrate. It is characterized by:

Further, in the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, in the method for manufacturing a nonvolatile semiconductor memory device, the implantation amount of impurity ions in a direction perpendicular to the semiconductor substrate is 1E15 / cm ² or more. It is characterized by being.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, in the method of manufacturing a nonvolatile semiconductor memory device, there is provided a method of manufacturing a semiconductor device, comprising the steps of: Is performed while rotating, and the amount of impurity ions implanted from the oblique direction is
It is not more than 1E14 / cm ² .

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a nonvolatile semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, a semiconductor memory device is called a split gate type flash memory, and has a first source portion 4 on a bottom surface 3 of a groove 2 formed on a semiconductor substrate 1 as a source.
The second source portions 6 are formed on the side surfaces 5 respectively. The impurity concentration of the second source portion 6 formed on the side surface 5 of the groove 2 is low and shallow, and the overlap with the gate is 0.0%.
The channel length is suppressed to about 5 μm and the channel length is shorter than that of the conventional split gate type flash memory. When formed by the conventional method, the overlap between the source and the gate is about 0.15 μm.

On the other hand, by increasing the impurity concentration of the first source portion 4 formed on the bottom surface 3 of the groove 2, the resistance of the source line is reduced and the ON current can be increased. Further, the first source part 4 and the drain 7 may be silicided with titanium or the like in order to increase the ON current. However, at this time, it is necessary to prevent the side surface of the control gate 8, the side surface of the floating gate 9, and the region of the second source portion 6 from being silicided.

Next, a method of manufacturing the nonvolatile semiconductor memory device of FIG. 1 will be described in detail with reference to FIGS. First,
After forming an element isolation insulating film (not shown) on the semiconductor substrate 1, as shown in FIG. 2, a first insulating film 11 (about 80 to 100 °) serving as a tunnel gate insulating film is formed. A first conductive layer 9 (about 1500 °) serving as a floating gate is formed on one insulating film 11. Next, a first poly-poly insulating film 12 (silicon oxide film + silicon nitride film + silicon oxide film,
(About 200 °).

Next, as shown in FIG. 3, the first inter-poly insulating film 12, the first conductive layer 9, and the first insulating film 11 are patterned. At this time, the first conductive layer 9
Is the first channel 13 serving as the channel of the memory cell section.
It is removed from the second channel 14 which remains on the second channel 14 and becomes the channel of the selection transistor section. Next, a second insulating film 15 (200 to 3) is formed on the second channel 14.
Then, a second poly-poly insulating film 16 is formed on the side surface of the first conductive layer 9.

Next, as shown in FIG. 4, a second conductive film serving as a control gate is formed on the second insulating film 15, the first poly-poly insulating film 12, and the second poly-poly insulating film 16. Layer 8 (polysilicon + tungsten silicide, 1
(About 500 + 1500 °). Next, as shown in FIG. 5, the second conductive layer 8, the first inter-poly insulating film 12, the second inter-poly insulating film 16, and the first
Conductive layer 9 and second insulating film 15 and semiconductor substrate 1
Are simultaneously etched to form a control gate 8 and a floating gate 9, and a groove (about 2000 to 3000) is formed on the semiconductor substrate 1 in a region serving as a source.
Å) is formed.

Next, as shown in FIG. 6, arsenic is vertically injected into the semiconductor substrate 1 using the control gate 8 as a mask to form a first source portion 4 and a drain 7. At this time, the injection amount is desirably set to about 1E15 to 7E15 / cm ² .

Next, as shown in FIG. 7, while rotating the semiconductor substrate 1, 3E1
Implantation of about 3 to 1E14 / cm ^{2 is performed} to form a thin and shallow second source portion 6 on the side surface 5 of the groove 2. The implantation angle at this time is preferably about 30 degrees with respect to the direction perpendicular to the semiconductor substrate. Thereafter, an interlayer film, a contact, a wiring, and the like are formed by a known method as shown in the right column of page 4 of JP-A-6-350095, whereby the nonvolatile semiconductor memory according to the embodiment of the present invention is formed. A device is formed.

[0028]

As described above, in the nonvolatile semiconductor memory device of the present invention, the source region is formed on the bottom and the side of the groove formed on the semiconductor substrate, and the impurity concentration on the bottom of the groove is increased. By setting the impurity concentration on the side surface of the groove to be low and shallow, the spread of the impurity to the channel region is suppressed small, and the channel length is formed shorter than that of the conventional split gate flash memory. Therefore, a nonvolatile semiconductor memory device having a small cell area can be obtained while high-speed reading is possible.

Further, according to the present invention, the above-mentioned nonvolatile semiconductor memory device can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining the method of manufacturing the nonvolatile semiconductor memory device in FIG. 1;

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the nonvolatile semiconductor memory device in FIG. 1;

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the nonvolatile semiconductor memory device in FIG. 1;

FIG. 5 is a cross-sectional view for explaining the method of manufacturing the nonvolatile semiconductor memory device in FIG. 1;

FIG. 6 is a cross-sectional view for explaining the method of manufacturing the nonvolatile semiconductor memory device in FIG. 1;

FIG. 7 is a cross-sectional view for explaining the method of manufacturing the nonvolatile semiconductor memory device in FIG. 1;

FIG. 8 is a cross-sectional view for explaining a conventional split gate flash memory.

FIG. 9 is a cross-sectional view for explaining a conventional stack type flash memory.

FIG. 10 is a diagram illustrating a method for manufacturing a conventional split gate flash memory.

FIG. 11 is a diagram illustrating a method of manufacturing the split gate flash memory in FIG.

FIG. 12 is a diagram illustrating a method of manufacturing the split gate flash memory in FIG.

FIG. 13 is a diagram illustrating a method of manufacturing the split gate flash memory in FIG.

FIG. 14 is a diagram illustrating a method of manufacturing the split gate flash memory in FIG.

15 is a diagram illustrating a method of manufacturing the split gate flash memory in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Groove 3 Bottom surface 4 Source (first source part) 5 Side surface 6 Second source part 7 Drain 8 Second conductive layer (control gate) 9 First conductive layer (floating gate) 10 Non-volatile semiconductor Storage device 11 First insulating film 12 First interpoly insulating film 13 First channel 14 Second channel 15 Second insulating film 16 Second interpoly insulating film 50 Split gate type flash memory 51 Stacked flash memory

Claims (6)

[Claims] A second conductive type source and a drain formed on a main surface of a first conductive type semiconductor substrate; a first channel region formed between the source and the drain; A channel region, a tunnel gate insulating film formed on the first channel region, a select gate insulating film formed on the second channel region, and a floating gate formed on the first channel When,
An inter-poly insulating film formed on the floating gate, a control gate formed on the inter-poly insulating film, and a select gate formed on the select gate insulating film; The gate is electrically connected and the floating gate is electrically insulated, and the source is formed in a groove which is recessed in the substrate from the main surface of the semiconductor substrate forming the drain. Nonvolatile semiconductor memory device. 2. The non-volatile semiconductor memory device according to claim 1, wherein said source includes a first source portion formed on a bottom surface of said groove, and a second source portion formed on a side surface of said groove. A nonvolatile semiconductor memory device comprising: 3. The nonvolatile semiconductor memory device according to claim 2, wherein said first source portion has an impurity concentration of said second source portion.
A nonvolatile semiconductor memory device having an impurity concentration higher than that of the source portion. 4. The method according to claim 1, wherein the first conductive type semiconductor substrate has
Forming a first insulating film serving as a tunnel gate insulating film, forming a first conductive layer serving as a floating gate on the first gate insulating film, and forming a first conductive layer on the first conductive layer; Forming a second insulating film, etching the second insulating film and the first conductive layer, and forming a third insulating film on a second channel region and a side surface of the first conductive layer. Forming a second conductive layer serving as a control gate and a select gate on the second insulating film and the third insulating film; and forming the second conductive layer and the second Simultaneously etching the insulating film and the third insulating film, the first conductive film, and the semiconductor substrate; implanting impurity ions in a direction perpendicular to the semiconductor substrate; Diagonal to semiconductor substrate Method of manufacturing a nonvolatile semiconductor memory device characterized by a step of injecting from. 5. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein an implantation amount of impurity ions from a direction perpendicular to said semiconductor substrate is 1E15 / cm ² or more. A method for manufacturing a semiconductor storage device. 6. The method of manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein the impurity ions are implanted into the semiconductor substrate from an oblique direction while rotating the semiconductor substrate. A method of manufacturing a nonvolatile semiconductor memory device, wherein an implantation amount of impurity ions from the semiconductor device is 1E14 / cm ² or less.